Block synthesis in Synopsys DC

[zhanch]

just wonder whether synopsys DC can do block synthesis. For example, there are serveral modules are the same. Can we ask DC just to synthesis one module, and others using the same netlist and sdf.
Actually, I know synplify ASIC can do this, not sure whether synopsys can do in the same way.

Many thanks,

 

[jackson_peng]

block synthesis

the netlist can be shared if you try a bottom-up synthesis flow.

as for the SDF, i believe it should be merged into the top design, which means most hierarchy name should be prefixed.

 

[ami]

Re: block synthesis

Hi,
Sure that you can do this in the synthesis process (using DC)! but remember to "uniquify" at the TOP level.
Rgrds,

 

[rameshsuthapalli]

Re: block synthesis

just wonder whether synopsys DC can do block synthesis. For example, there are serveral modules are the same. Can we ask DC just to synthesis one module, and others using the same netlist and sdf.
Actually, I know synplify ASIC can do this, not sure whether synopsys can do in the same way.

Many thanks,

for doing the block level u must do the uniqufication frist .
so that it will duplicate the cells accordingly. and it will also duplicate the sdf file.
so that u will get the uniqufied netlist and sdf file which consist of all cell delays and cells.