Block level place and route

[anwei7208]

place and route big blocks

I'm a newbie. Please help!

I've finished the verilog coding for a chip consisting of several big blocks. SOC encounter offers partition approach of place and route. The doc says there are top-down or bottom-up approaches. It seems to be easier for me to go bottom-up approach.

My question is: When I work on each block, do I need to finish complete place and route including power planning and CTS before I move to top-level chip assembly? If so how to do power planning on block level?

The encounter doc is very unclear on block level place and route. Is there a nice tutorial on this issue?

Thanks very much!

 

[semi_jl]

Yes. You had better complete P&R in block. And then in top level, all the blocks can be instanced as macros.

In general, the power planning for block is nothing in particular. You need only to give a power supply to them in top level, as the macros in your design.

 

[ee171]

is there any tutorial that shows using macro blocks like ram? Thanks.

 

[dementu666]

I would do it in one run and not for separate blocks!

If you do P&R for each block you will have to define timing constraints for each block and the tool cannot optimize the logic at the borders of you modules!
Besides this, if the floorplan/power routing changes for one module you might have to modify several other scripts at different modules!

If you do it in one run, yes it will be more work to do at floorplanning, power planning... But you only have to define 1 sdc file, 1 floorplan, 1 power routing!
Even the clock tree will be better as the tool can optimize it better!

I say this as I understood you are the only designer working on this! When you work in large projects and several engineers have to do this in parallel then block P&R is the right way to do it!

Good luck!
C.