module bitunstuffing(clk,rst,en,data_in,data_out,data_valid);
input clk,rst,data_in,en;
output data_out,data_valid;
wire clk,rst,data_in,en;
reg data_out;
reg [3:0] count;
reg data_valid; //Signal to determine whether data_out is valid or not
always@(posedge clk)
begin
if(rst)
begin
data_out<=1'b0;
data_valid<=1'b1;
count<=4'b0;
end
else
begin
if(en)
begin
data_out<=data_in;
if(data_in) //Counter Logic
begin
count<=count+1;
end
else
begin
count<=4'b0;
end
if(count==4'b0110) //If count equals 6
begin
data_valid<=1'b0;
count<=4'b0;
end
else
begin
data_valid<=1'b1;
end
end
end
end
endmodule