Yes, many of them. But not for Flash-ADC or Folding-ADC.
Because of the timing and skew issues both above need S/H in the +GS/s range. So power efficiency indicate to use parallel pipeline.
The key to all high performance ADC is that with calibration you can violate matching dimensioning and being noise limited. Furtheron you can tolerate in some architectures also decision errors bringing also the S/N, and therefore power down.
Flash and Folding are not easy to calibrate!