bit synchronization in Folding ADC

[kickbeer]

bit synchronization

I'm having a difficulty how i can precisely synchronize the 5 bits from fine converter and 3 bits from coarse converter..Can somebody show me how to do that?

 

[rfsystem]

folding adc

Do you mean synchronization in time domain?

Folding converte operate like pipeline adc stages . The difference is that the radix operation is done not in time sequence. So the MSB and LSB parts are evaluated at the same sample. That requires a sample and hold circuit in front.

 

[kickbeer]

what is bit sync adc

yes. in time domain because the is different delays along the coarse and the fine signal paths.

I read some article and they don't use sample and hold and just the bit synchronization. But they do not explain how the synhronization done.

do you have idea?

 

[rfsystem]

bit synchronization in folding adc

I did not know any other solution than to match the time delay of the input signal and the first stage output. But any small mismatch in between would violate the ENOB at higher frequencies.

But also in a pure Flash-ADC the S/H help to avoid issue because you have skew in the layout and the reference ladder.

 

[kickbeer]

how to synchronize fine and coarse converter

do you have implemented Sample and hold before?

 

[rfsystem]

adc 19 bit

Yes, many of them. But not for Flash-ADC or Folding-ADC.


Because of the timing and skew issues both above need S/H in the +GS/s range. So power efficiency indicate to use parallel pipeline.

The key to all high performance ADC is that with calibration you can violate matching dimensioning and being noise limited. Furtheron you can tolerate in some architectures also decision errors bringing also the S/N, and therefore power down.

Flash and Folding are not easy to calibrate!

 

[kickbeer]

Yes, many of them. But not for Flash-ADC or Folding-ADC.


Because of the timing and skew issues both above need S/H in the +GS/s range. So power efficiency indicate to use parallel pipeline.

The key to all high performance ADC is that with calibration you can violate matching dimensioning and being noise limited. Furtheron you can tolerate in some architectures also decision errors bringing also the S/N, and therefore power down.

Flash and Folding are not easy to calibrate!

The speed of Folding ADC i'm going to have is around 80 MSamples. Is that correct to say, the more speed our ADC has, then it would be more difficult to calibrate Sample and Hold?

Thx