wire [2:0] signs;
wire [2:0] output_signs;
wire control;
assign output_signs = control ? signs [2:0] : signs [0:2];
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};
Hi,
Honestly I don't know.
But what speaks against trying it? A simulation should be rather simple...and should be done anyway.
I expect it to work.
What confuses me is the naming.
"Sign" usually shows whether the value is positive or negative.
Sign[2:0] ... sounds as if there are 3 sign bits, but no value
Klaus
The above link does not allow to download free.My favourite reference is the Verilog IEEE 1364 standard respectively the SystemVerilog IEEE 1800 replacing the former. Bit concatenation syntax is a rather basic point covered by many tutorials and text books.
The recent IEEE 1800-2017 version is available for free by the IEEE Get program https://ieeexplore.ieee.org/document/8299595
What you are trying to state is not understood. Can you please elaborate more so that what you want to state becomes clear.It appears it was removed from the IEEE get program. I assume Acellera (who I think was the sponsor) ended their sponsorship of the specification.
But why signs[0:2] raise an error?I thought 2 weeks should be sufficient to answer the question yourself. I expect that signs[0:2] is raising an error.
I was stating that the IEEE get program allows normally paid for IEEE specs to be downloaded for FREE, but they are FREE because some company pays for your download (by sponsoring it). Acellera (I think) used to be the sponsor for the IEEE spec for Systemverilog at least up to last year some time. I haven't downloaded it recently so don't know when they stopped.What you are trying to state is not understood. Can you please elaborate more so that what you want to state becomes clear.
No only one of the examples you have will work correctly.Will both the two ways of reversing bits which has been shown in post number 1 will work correctly?
wire [2:0] signs;
signs[0:2]
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};
How can we say that signs no longer matches the definition of bit order as SystemVerilog LRM does not talk anything of bit reversal and SystemVerilog LRM also mention anything of bit order when a signal/variable is declared as vector like signs[0:2] is a three bit vector.You can't define:
and then access it withCode:wire [2:0] signs;
signs no longer matches the definition of the bit order.Code:signs[0:2]
But this code is same as one of my codes for bit reversal. Is not it?This is the concatenation code I was referring to that uses &:
other versions of your bit-reversal violated the Verilog language rules.Code:assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};
Because it doesn't match. Is signs[2:0] the same as signs[0:2]? Signs is defined as having a bit range of [2:0]. You can bit slice it with any range where the left index is higher than the right index. Swapping to have the right index larger than the left doesn't match the original definition.How can we say that signs no longer matches the definition of bit order as SystemVerilog LRM does not talk anything of bit reversal and SystemVerilog LRM also mention anything of bit order when a signal/variable is declared as vector like signs[0:2] is a three bit vector.
Yes it was the same code, I was just pointing out that is the only valid code you wrote to perform a bit reversal. All your other attempts are not valid and violate the vector bit order direction that was declared in the definition of the signals.But this code is same as one of my codes for bit reversal. Is not it?
There are wires and an assignment statement to get the reverse of the bits for signs and output_signs should eith het the signs in same order or in reverse order as follows
Code:wire [2:0] signs; wire [2:0] output_signs; wire control; assign output_signs = control ? signs [2:0] : signs [0:2];
Will the above Verilog code work and have no issues?
Will the above Verilog code work and no issues will be the if the above assignment statement is replaced as follows:
Code:assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};
module test(input [3:0]in,
input clk,
output reg[3:0]out1,out2,out3,out4);
//-----------------------------Declaring parameters---------------------------
parameter[1:0] s0=0,s1=1,s2=2,s3=3;
reg [1:0]state;
//---------------------------Initializing state-------------------------------
initial state<=s0;
always@(posedge clk) begin
case(state)
//-------------------------------Declaring cases------------------------------
s0: begin out1<={in[0],in[1],in[2],in[3]}; state<=s1; end
s1: begin out2<={in[0],in[1],in[2],in[3]}; state<=s2; end
s2: begin out3<={in[0],in[1],in[2],in[3]}; state<=s3; end
s3: begin out4<={in[0],in[1],in[2],in[3]}; state<=s0; end
default: begin out1<=4'h0; out2<=4'h0; out3<=4'h0; out4<=4'h0; end
endcase
end
endmodule
Testbench:
module tb();
reg [3:0]in;
reg clk;
wire [3:0]out1,out2,out3,out4;
test i1(in,clk,out1,out2,out3,out4);
always #5clk=~clk;
initial begin
clk=0;
$dumpfile("tb.vcd");
$dumpvars;
$monitor("output1=%b output2=%b output3=%b output4=%b",out1,out2,out3,out4);
#4 in=4'b1010;
#50 $finish;
end
endmodule
output1=xxxx output2=xxxx output3=xxxx output4=xxxx
output1=0101 output2=xxxx output3=xxxx output4=xxxx
output1=0101 output2=0101 output3=xxxx output4=xxxx
output1=0101 output2=0101 output3=0101 output4=xxxx
output1=0101 output2=0101 output3=0101 output4=0101
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