fragnen
Full Member level 3
There are wires and an assignment statement to get the reverse of the bits for signs and output_signs should eith het the signs in same order or in reverse order as follows
Will the above Verilog code work and have no issues?
Will the above Verilog code work and no issues will be the if the above assignment statement is replaced as follows:
Code:
wire [2:0] signs;
wire [2:0] output_signs;
wire control;
assign output_signs = control ? signs [2:0] : signs [0:2];
Will the above Verilog code work and have no issues?
Will the above Verilog code work and no issues will be the if the above assignment statement is replaced as follows:
Code:
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};