# bit reversal in Verilog

#### fragnen

##### Member level 5
There are wires and an assignment statement to get the reverse of the bits for signs and output_signs should eith het the signs in same order or in reverse order as follows

Code:
wire [2:0] signs;
wire [2:0] output_signs;
wire control;

assign output_signs = control ? signs [2:0] : signs [0:2];
Will the above Verilog code work and have no issues?

Will the above Verilog code work and no issues will be the if the above assignment statement is replaced as follows:

Code:
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};

#### KlausST

##### Super Moderator
Staff member
Hi,

Honestly I don't know.

But what speaks against trying it? A simulation should be rather simple...and should be done anyway.
I expect it to work.

What confuses me is the naming.
"Sign" usually shows whether the value is positive or negative.
Sign[2:0] ... sounds as if there are 3 sign bits, but no value

Klaus

#### fragnen

##### Member level 5
Hi,

Honestly I don't know.

But what speaks against trying it? A simulation should be rather simple...and should be done anyway.
I expect it to work.

What confuses me is the naming.
"Sign" usually shows whether the value is positive or negative.
Sign[2:0] ... sounds as if there are 3 sign bits, but no value

Klaus
The problem may come during synthesis. Simulation may work. The name can be changed from existing signs. Let someone else reply.

#### FvM

##### Super Moderator
Staff member
The question can be easily answered by reviewing the Verilog language reference manual. Is it a correct bit concatenation expression? If so, what are you worrying about?

#### fragnen

##### Member level 5
FvM
Can you please let me know what Verilog reference manual states on this? What is being worried whether this is correct in doing in Verilog as the book which is being referred does not state in this regard.

#### FvM

##### Super Moderator
Staff member
My favourite reference is the Verilog IEEE 1364 standard respectively the SystemVerilog IEEE 1800 replacing the former. Bit concatenation syntax is a rather basic point covered by many tutorials and text books.

The recent IEEE 1800-2017 version is available for free by the IEEE Get program https://ieeexplore.ieee.org/document/8299595

#### fragnen

##### Member level 5
My favourite reference is the Verilog IEEE 1364 standard respectively the SystemVerilog IEEE 1800 replacing the former. Bit concatenation syntax is a rather basic point covered by many tutorials and text books.

The recent IEEE 1800-2017 version is available for free by the IEEE Get program https://ieeexplore.ieee.org/document/8299595

There is no mistake in bit concatenation format. There may be mistake in getting the reverse assignment of bits. Please comment.
--- Updated ---

I got the above document, but not from that link. Where is the relevant section to look out for this in this document as it is a big document and some of the sections discusses about concatenation in this doc, but still did not obtain the relevant section. Can you please indicate which page is it in this document?

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##### Super Moderator
Staff member
It appears it was removed from the IEEE get program. I assume Acellera (who I think was the sponsor) ended their sponsorship of the specification.

There is no specific section devoted to bit-reversal. You perform bit reversal either using the concatenation operation & or by using a for loop to assign the bits in reverse order.

#### fragnen

##### Member level 5
It appears it was removed from the IEEE get program. I assume Acellera (who I think was the sponsor) ended their sponsorship of the specification.
What you are trying to state is not understood. Can you please elaborate more so that what you want to state becomes clear.

Will both the two ways of reversing bits which has been shown in post number 1 will work correctly?

#### FvM

##### Super Moderator
Staff member
I thought 2 weeks should be sufficient to answer the question yourself. I expect that signs[0:2] is raising an error.

#### fragnen

##### Member level 5
I thought 2 weeks should be sufficient to answer the question yourself. I expect that signs[0:2] is raising an error.
But why signs[0:2] raise an error?

##### Super Moderator
Staff member
What you are trying to state is not understood. Can you please elaborate more so that what you want to state becomes clear.
If you want to understand the IEEE get program read the information you can find on the link that was posted in #6 by FvM. As you are asking me to clarify it is apparent you didn't read about the IEEE get program and only attempted to download the PDF.

Will both the two ways of reversing bits which has been shown in post number 1 will work correctly?
No only one of the examples you have will work correctly.

You can't define:
Code:
wire [2:0] signs;
and then access it with
Code:
signs[0:2]
signs no longer matches the definition of the bit order.

To perform a bit-reversal in Verilog/Systemverilog, either perform concatenation using & or use a for loop.

This is the concatenation code I was referring to that uses &:
Code:
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};
other versions of your bit-reversal violated the Verilog language rules.

The other option is to use a for loop and perhaps put it in a function to make it easier to use. I won't post code as there are numerous code samples for using for loops in Verilog on the web.

### fragnen

points: 2

##### Super Moderator
Staff member
It just dawned on me that I should have been saying use , (comma not &) for the concatenation. I've been working on a VHDL design and was thinking in terms of VHDL concatenation. Sorry if that was confusing.

#### fragnen

##### Member level 5
You can't define:
Code:
wire [2:0] signs;
and then access it with
Code:
signs[0:2]
signs no longer matches the definition of the bit order.
How can we say that signs no longer matches the definition of bit order as SystemVerilog LRM does not talk anything of bit reversal and SystemVerilog LRM also mention anything of bit order when a signal/variable is declared as vector like signs[0:2] is a three bit vector.

This is the concatenation code I was referring to that uses &:
Code:
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};
other versions of your bit-reversal violated the Verilog language rules.
But this code is same as one of my codes for bit reversal. Is not it?

##### Super Moderator
Staff member
How can we say that signs no longer matches the definition of bit order as SystemVerilog LRM does not talk anything of bit reversal and SystemVerilog LRM also mention anything of bit order when a signal/variable is declared as vector like signs[0:2] is a three bit vector.
Because it doesn't match. Is signs[2:0] the same as signs[0:2]? Signs is defined as having a bit range of [2:0]. You can bit slice it with any range where the left index is higher than the right index. Swapping to have the right index larger than the left doesn't match the original definition.
The LRM does discuss bit ordering of vectors somewhere, perhaps in section about bit slicing.

But this code is same as one of my codes for bit reversal. Is not it?
Yes it was the same code, I was just pointing out that is the only valid code you wrote to perform a bit reversal. All your other attempts are not valid and violate the vector bit order direction that was declared in the definition of the signals.

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### fragnen

points: 2

#### VerLearn

##### Newbie level 5
There are wires and an assignment statement to get the reverse of the bits for signs and output_signs should eith het the signs in same order or in reverse order as follows

Code:
wire [2:0] signs;
wire [2:0] output_signs;
wire control;

assign output_signs = control ? signs [2:0] : signs [0:2];
Will the above Verilog code work and have no issues?

Will the above Verilog code work and no issues will be the if the above assignment statement is replaced as follows:

Code:
assign output_signs = control ? signs [2:0] : {signs [0], signs[1], signs[2]};

The problem with your statement is a[m:n] and a[n:m] are not treated the same in Verilog. You can select a part of the array instead, say a[0]. I don't have a problem as I'm picking an element from the array. Now, the idea is to pick all the elements individually reverse concatenate them. It works. Here is the sample code.

Code:
module test(input [3:0]in,

input clk,

output reg[3:0]out1,out2,out3,out4);

//-----------------------------Declaring parameters---------------------------

parameter[1:0] s0=0,s1=1,s2=2,s3=3;

reg [1:0]state;

//---------------------------Initializing state-------------------------------

initial state<=s0;

always@(posedge clk) begin

case(state)

//-------------------------------Declaring cases------------------------------

s0: begin out1<={in[0],in[1],in[2],in[3]}; state<=s1; end

s1: begin out2<={in[0],in[1],in[2],in[3]}; state<=s2; end

s2: begin out3<={in[0],in[1],in[2],in[3]}; state<=s3; end

s3: begin out4<={in[0],in[1],in[2],in[3]}; state<=s0; end

default: begin out1<=4'h0; out2<=4'h0; out3<=4'h0; out4<=4'h0; end

endcase

end

endmodule

Testbench:

module tb();

reg [3:0]in;

reg clk;

wire [3:0]out1,out2,out3,out4;

test i1(in,clk,out1,out2,out3,out4);

always #5clk=~clk;

initial begin

clk=0;

$dumpfile("tb.vcd");$dumpvars;

$monitor("output1=%b output2=%b output3=%b output4=%b",out1,out2,out3,out4); #4 in=4'b1010; #50$finish;

end

endmodule
Results:
output1=xxxx output2=xxxx output3=xxxx output4=xxxx
output1=0101 output2=xxxx output3=xxxx output4=xxxx
output1=0101 output2=0101 output3=xxxx output4=xxxx
output1=0101 output2=0101 output3=0101 output4=xxxx
output1=0101 output2=0101 output3=0101 output4=0101

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