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[SOLVED] Big EMI issue on LCD screen

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Advanced Member level 1
Jan 22, 2014
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Hello guys,

I have designed a display board to interface LVDS signal coming from a camera to parallel RGB interface LCD screen input.

The displayboard does not have any EMI problem. However when i connect it to the LCD screen thought a flat cable, a big EMI interference is coming out of the flat cable. The frequency of this EMI is at 25MHz and it has harmonics every 25MHz up to 700MHz. The 25 MHz is the pixel clock of the RGB data

I tried to reduce the EMI changing the values of the series termination resistors, i added more bypass capacitors, i place finger contacts to have more direct gnd contacts between the LCD screen and the display board....and i got some improvements but still the EMI levels are high.

Any idea to improve the current EMI results?

Thanks in advance.



Usually LVDS causes low EMI, thus I expect the problem else where.
We need to see the schematic, the PCB layout and wiring.


My understanding is that the cable to the LCD is parallel and not LVDS in this setup.
What pinout did you use for the cable? Did you insert ground lines between the signal lines?

Hi Thanks a lot for your quick anwers.

I can not share the schematics but see below a block diagram about the approach:


The flat cable and pinout is given by the LCD manufacturer and I cano not changed it:


The output of the FPGA looks like this


The datasheet of the LCD screen shows the next pin configuration:





The PCB looks like this:



There tracks between the FPGA output and the LCD connector have controlled impedance at 50Ohm and all of them have a tunning length:


--- Updated ---

For more information, the LCD Screen has a flat cable which is given by the manufacturer and it can not be replaced:


The EMI source is the flat calbe together with the connector. But I dont know what else to do to reduce the EMI levels. This EMI levels are also inducted on the black calbe of the previous picture which it is the SerDes Link.

I have a couple of more ideas i want to share with you to check your opinions:

1) Add and EMI filter at the ouput of the POC (Power Over Coax) filter to avoid EMI interferences on the black cable.

2) Add the following EMI filter of TI between the output of the level shifters (FPGA) and the connector inputs:


However I am afraid to have signal integrity problems when I am adding this filters and have another issue on the frames. I experienced some image artifacts when i tried to place an RC filter (silimar like the one of the Texas Instruments by hand-made) on the RGB parallel interface...

What do you think? Any idea?

Thanks in advance.

Last edited:


I don't know the length and type of cable... and wheter they are shielded..

I see power_GND, but no signal_GND to the 26+ signals ... most probably with identical switching edges.
All the "switching edge" current needs a return path. And the return path needs to be close to the signals for the return current to compensate the signal current. This (close return path) also reduces overall impedance and improves noise immunity.

You can do a simple test:
* use the identical mechanical setup as the real application.
* then use a scope
* connect the scope jig GND to tge GND of the PCB
* connect the scope jig signal to the display GND check the GND bounce between both.
I guess there is a lot of noise.


Hi Thanks a lot for your quick reply. I measured the noise and it is not noisy as I could expected. I dont have the schematics of the LCD screen. But it is a flex pcb and the flat cable you see in the following image belongs to the flex pcb:


So I can not change anything here.

On the other hand, see below the EMI results of the EMI/EMC lab:


At the moment I am totally out of ideas about how to reduce those peaks...



Still don't know length.
Do you have a metal frame? Metal case? Shielding?

Why are the series resistors 39 Ohms? I guess this has nothing to do with trace impedance.
Also what are the meanders for? For 25MHz signals I doubt you need it ... and they are also a lot of meanders for the most lengthy signal traces. I don't understand.



The length of the RGB tracks are tunning at 150mm. And the meanders are to adjust the length between the different RGB data lines. On this way the data lanes have the same length.

The series termination resistors of 39ohm were selected after doing some real tests. With 39 Ohm i was able to reduce the EMI peaks. Signal integrity simulation can not be done as far as i don't have the ibis model of the LCD screen flex PCB.

You are right, for 25MHZ maybe is not needed to do any length tunning or placing series termination resistors. But it was a layout recommendation of the manufacturer of the LCD screen and the first Prototype of my displayboard was designed without doing any tunning length on the RGB data lanes and it did not work...

This is the second iteration of the displayboard and it is working fully stable but i have the previous EMI issues.


Series resistors like 33 to 39 ohm are typically used to achieve source side termination, adding up to total 50 or 60 ohms with driver output impedance.

The schematics are unclear to me in several regards. How many signals switching with 25 MHz clock? Where's the pixel clock driver? Really no display ground connection?

Measures that might help
- well chosen ferrite beads instead of the series resistor termination, particularly for pixel clk
- common mode flat cable ferrite
- spread spectrum clock

Suppose you mounted the digital board onto the monitor directly - like replace the ribbon cable with a "zero length" connector, maybe sex-swap the one on the board you can mod easiest. Then put a can around it all.

Awkward mechanicals can be fixed later, yes?

Again: metal frame, shielding, mounting???
--> No update regarding EMI from my side.

A 25MHz signal has about 10,000 mm wavelength.
Thus the use of the meanders is questionable. I rather expect that malfunction came from a general signal-to-clock timing problem. While the picoseconds of the meanders may improve the situation .. I expect it will hit you later again.--> compare datasheets about timing.


you might also try a flat oval CM ferrite at each end of the cable - as the RFI is radiated in this case - this may well be a solution,


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Metal frame or shielding of the cable helps to reduce a bit the levels of the EMI but they still are very high. On the other hand, for serial production is not realistic to provide a frame, because we need to sell the display without any shielding like the next image:


I was checking datasheet and timings are not the route cause. I checked again the GND power pins of the LCD screen and they are very noisy. It could be that they are the root of the problem:


When I disconnnect the flat cable from the connector, the noise is gone. Howerver when I connected again the complete noise is spreaded along the GND plane of the displayboard. I was thinkin to use a ferrit bead or choke to remove to separate the power GND pins of the LCD screen from the GND plane of my displayboard. However with that approach, I am splitting the GNDs and according to the design rules of the LCD screen, Power GND pins and the Displayboard GND plane should be the same GND....Any idea?



a ferrite bead may reduce the noise, but...
...since the GND is the reference for the digital signals I expect signal (level, timing) problems.


Attaching the cable attaches 25 loads to 25 drivers and they all dump and pump that charge to / from ground every edge.

You might play with those source termination resistors and raise value (since unlikely there is any controlled impedance being matched) to play instead with simple RC. Keep the impulse current amplitude lower and wider, just not so much that you compromise timing. Maybe a bit less filter on the clock than the slower data.
Cut and try until you start trading the problem you've got for a new one, then back up two steps.

Maybe a bit less filter on the clock than the slower data.
I thought the other way round.
Slow down the clock to get more data_setup_time.

But indeed it depens on the whole timing, but we neither know the transmitter timing nor the LCD timing.
The OP just states "timings are not the route cause".


I was thinkin to use a ferrit bead or choke to remove to separate the power GND pins of the LCD screen from the GND plane of my displayboard.

According to interface list, the display has 5 GND pins, don't know why they are designated "Power Ground", apparently there are no other signal returns. Separating LCD ground from interface board will cut the return path, possibly cause data corruption and very likely further increase EMI.

Instead of breaking the return path, you want to force the return current into the flat cable and block other current paths. If LCD board and cable layout can't be modified, common mode chokes as suggested in post #9 and #13 are the only way to reduce radiation from the cable.

The other option is to taylor the spectrum of clock and data signals. It's not necessary that the spectrum of a 25 MHz clock spans 200 or even 700 MHz bandwidth. The interesting question is how much DCLK rise- and falltime presented to the given LCD device can be increased without transmission failure. Data sampling window is large enough (at least 10-15 ns) to allow some timing uncertainty.


Thank you again for your answers. I would like to understand better the concept of spreading the clock spectrum.
I am using a FPGA to generate the pixel clk and this FPGA has the possibility of constraining the slew rate of every IO. There are three levels of configurations: low, normal and fast. At the moment is confugured in normal. Changing the slew rate of the clk, would it change the clk spectrum? Or should I implement some kind of the FPGA modulator IP core to change spectrum of the clk?

Thanks in advance

As far as I understand RGB data lines driven by level converters, FPGA slew rate is irrelevant then. DCLK source isn't shown in the posted schematics.

If the LCD interface can be driven by spread spectrum clock depends on the display requirements. The modulation parameters should be optimized for the quasi-peak detector characteristics and detector bandwidth specified for EMI measurements to achieve maximal peak reduction.

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