Thanks both Marce and FvM!
I came across a book from Intel that for PCIe, they did not explicitly required a certain impedance for the trace, and they mentioned as long as the differential trace stay in 100ohm +- 20%, it would give correct outcome. Forgive me for my ignorant, isn't this statement kind of vague? How to get an impedance by not using the usual microstrip or stripline configuration?
I do understand that as long as the eye pattern yields acceptable result within margin, the impedance doesn't matter at all for PCIe.
For the attached pic, I found that the planes below is cut nicely according to the dimension of the main switching route. Do we have to consider the fringe of field that may possibly couple to the GND plane too?
---------- Post added at 09:43 ---------- Previous post was at 09:06 ----------
"Dual stripline — in this case the two signal conductors are sandwiched between the two reference planes on adjacent layers. These two signal layers will be routed orthogonally to minimise inter-layer crosstalk; i.e. the signal layers are made to cross at right angles so as to minimise the crossing area. The structure is then behaving as two independent offset striplines." as quoted from Polar Instruments.
This is the image for the differential pairs of PCIe on L4 which you can find that some of the differential pairs overlap with the traces or even plane on L3. In fact other single-ended lines also overlap with the plane at L3 for a quite long distance, 2cm above.
Eventually, eye pattern decides whether this routing methodology is feasible or not, I guess...