broussea
Newbie level 2
Hi,
I need to model an asynchronous memory for a processor fetch stage. Ideally, I'd like to represent the memory by a delay "D" between the output address pin and the input data pin of my design, so that this delay will be taken into account during synthesis and place&route.
I'm using Design Compiler for synthesis and SoC Encounter for place&route, and I have a very hard time identifying a common (and simple) way to realize this. Could anyone here give me some hints at how to do this? Is there any timing constraints that help to do this?
I need to model an asynchronous memory for a processor fetch stage. Ideally, I'd like to represent the memory by a delay "D" between the output address pin and the input data pin of my design, so that this delay will be taken into account during synthesis and place&route.
I'm using Design Compiler for synthesis and SoC Encounter for place&route, and I have a very hard time identifying a common (and simple) way to realize this. Could anyone here give me some hints at how to do this? Is there any timing constraints that help to do this?
