That is called functional verification. You provide various stimulus to your DUT via a test-bench and then observe the output signals how they behave, whether they are performing the intended functions or not.
A test-bench might not cover all the corner-cases of a design. This is where SystemVerilog and hardware verification comes in. They will simulate the DUT with all possible input vectors and observe the results. Lots of bugs can crop up in a designed DUT if it has not been carefully coded.