Hi all,
I am supposed to design an LDO with output voltage of 1.8V. should i first start with the block level simulation using MATLAB or verilog-A. how should i know how much gain i require for my error amplifier and BGR. can someone please explain.
Hi all,
I am supposed to design an LDO with output voltage of 1.8V. should i first start with the block level simulation using MATLAB or verilog-A. how should i know how much gain i require for my error amplifier and BGR. can someone please explain.
Hi, Chethan
I don't think you need a behavioral modeling for the LDO because it is really a simple circuits. If you do need a behavioral simulation, I suggest you use verilog-a language instead of matlab.
Sixth,
Could you showcase some verilog-a examples ? I think using LDO is a good example. It would be even better if the examples are illustrated with Cadence simulator.
Thanks.
Hi, Chethan
I don't think you need a behavioral modeling for the LDO because it is really a simple circuits. If you do need a behavioral simulation, I suggest you use verilog-a language instead of matlab.
Thanx sunking and sixth,
now to start with my design, i have nmos and pmos devices categorized as Logic , MM and RF. can someone explain what exactly Logic, MM and RF devices means. are they modelled differently??. cant i use an RF or logic device to design an LDO. any document regarding this would be very helpful.
Sixth,
Could you showcase some verilog-a examples ? I think using LDO is a good example. It would be even better if the examples are illustrated with Cadence simulator.
Hi, hoonsk
Maybe the first step of behavioral simulation is to answer a question about "why we need a behavioral model". One of the most important reason for behavioral modeling is its fast speed. We can simulate the circuit very quickly and change some critical parameters and simulate again untill we get a good result.
For a LDO, I think the most important part is the opamp. So, only the opamp need to be described with verilog-a language. Spectre provide a lot of behavioral module in its ahdlLib and you can find what you want. Otherwise, you can build your own verilog-a module by refer to the verylog-a Reference. For an opamp, you can discribe it through its transfer function using laplace_zp,laplace_zd,laplace_np or laplace_nd.
But if you had understand the principle of the LDO, you need not to do the behavioral simulation because this circuits is very simple and the simulator can handle it easily without any loose in speed.
sixth
Added after 10 minutes:
Chethan said:
Thanx sunking and sixth,
now to start with my design, i have nmos and pmos devices categorized as Logic , MM and RF. can someone explain what exactly Logic, MM and RF devices means. are they modelled differently??. cant i use an RF or logic device to design an LDO. any document regarding this would be very helpful.
Hi, Chethan
logic,MM and RF means different process. For digital design, you should use logic process, for analog and mixed signal design, the MM process should be used and for radio frequency project you should use RF process. For LDO, you should use MM process.
in ieee library, there are several papers on macromodel of ldo. it consit of resistor, capacitor, current source, voltage source, diode and so on. i also need these book. where can i find the book about macromdel of ldo?