Chethan
Full Member level 3

veriloga examples
Hi all,
I am supposed to design an LDO with output voltage of 1.8V. should i first start with the block level simulation using MATLAB or verilog-A. how should i know how much gain i require for my error amplifier and BGR. can someone please explain.
Hi all,
I am supposed to design an LDO with output voltage of 1.8V. should i first start with the block level simulation using MATLAB or verilog-A. how should i know how much gain i require for my error amplifier and BGR. can someone please explain.