[SOLVED] beginner in vhdl::code for frequency counter

[devika v kurup]

Hai,
I'm a beginner in VHDL coding and trying to write a code for frequency counter consisting of a clock divider ,count gate (AND gate), counter. I need a 1second clock as the output of clock divider. ise simulator is not responding while i create a 1second test bench. Could you help me to code the blocks?
THANK YOU.

 

[lucbra]

Google is your friend

 

[devika v kurup]

Here is my code.

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity clk_div is
    Port ( clk1 : in  STD_LOGIC;
           rst1 : in  STD_LOGIC;
           q1 : out  STD_LOGIC);
end clk_div;
 
architecture Behavioral of clk_div is
signal count:integer:=1;
begin
process(rst1,clk1)
begin
if(rst1='0')then
count<=0;
elsif(clk1'event and clk1='1')then
count<=count+1;
if(count>1000)then
count<=0;
elsif(count<=500)then
q1<='0';
elsif(count<=1000)then
q1<='1';
end if;
end if;
end process;
end Behavioral;

---

But i cant select second (s) for initial test bench lenght.
thanks for your valuable time.

 

[TrickyDicky]

why not write your own testbench?

 

[std_match]

If you are using normal clock frequencies it will take a very long time to simulate one second.
Use a shorter time for simulation and debugging.
When you have it working you can build it for 1 second and test it in a real FPGA.

 

[lucbra]

but then you will need to change the end value for some of your counters

 

[devika v kurup]

I made a test bench of 1000ns instead 1s. Now it is working and counts all the events in the unknown input. But i want the frequncy of unknown input. Clock frequncy=50MHz,ie 20ns, clk divider output frequency=1MHz ie, 1000ns. Can you verify and correct my code?

CLOCK DIVIDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_div is
    Port ( clk1 : in  STD_LOGIC;
           rst1 : in  STD_LOGIC;
           q1 : out  STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is

begin
process(rst1,clk1)


variable count:natural:=1;
begin

if rst1='0' then
count:=0;
q1<='0';
elsif clk1'event and clk1='1' then
count:=count+1;
if count<250 then
q1<= '0';
elsif count<500 then 
q1<='1';
else 
q1<='0';
end if;
end if;
end process;

end Behavioral;


GATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gate is
    Port ( q1 : in  STD_LOGIC;
           unk1 : in  STD_LOGIC;
           q2 : out  STD_LOGIC);
end gate;

architecture Behavioral of gate is

begin
process(q1,unk1)
begin

if(q1='1')then

q2<=q1 and unk1;
end if;

end process;
end Behavioral;




COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ctr is
    Port ( q2 : in  STD_LOGIC;
           rst1 : in  STD_LOGIC;
           q1 : in  STD_LOGIC;
             q3 : out  STD_LOGIC_vector(7 downto 0));
end ctr;

architecture Behavioral of ctr is

signal temp:std_logic_vector(7 downto 0):="00000000";
begin
process(q2,rst1)
begin
if(rst1='0' or q1='0')then
temp<="00000000";
elsif(q2'event and q2='1')then
if(q1='1')then
temp<=temp+1;
end if;

end process;
q3<=temp;
end Behavioral;