Question said:You can use MOS as capacitor. Add some capacitors between bandgap output and VSS.
electronrancher said:dragonslayer - this is a quite brilliant circuit, where did it come from? i would like to buy the book, or to get a copy of the class notes where this occurrs. can you PM me?
in exchange I will solve your problem. this circuit is a very clever implementation of a shunt bandgap reference. It gives an output voltage (at top of R2) of R2/R1*Vbg. In essence, it acts as a bandgap comparator where M1/M6 are the amplifier output and M5 is a big power device, shunting away current until voltage at the base of the npn is Vbg.
To answer your question, C1 is only used to compensate the amplifier to a dominant pole, not really to avoid output glitches. If you look at shunt references in general on Maxim or TI website, they usually have 1uf-10uf in parallel to R6 - this large capacitance is what is used to avoid output glitches. The internal capacitor C1 is used to compensate the amp, probably less than 10pf.
Let's assume the reference is in regulation. A bias current determined by the deltaVbe/R4 should be running through Q1, Q2, M2, M3 and therefore M1/M6 also. Using this current you can find the Rout of the M1/M6 pair.
Now since the master current is steered by Q1/Q2, we can say the gm of this amp is Ie(Q1)/kT/q or roughly Ic /.0259,
Gain of this first stage would be Gain1 = gm(q1) * Rout(M1) || Rout(M6). This gain can be increased by making M1 & M4 a multiple of M2/M3, which increases gm to k*gm where k means M1 is k times bigger than M2. In this manner, the M1/M6 amp can be given very big current gain. Make these transistors long or cascode them to give big Rout, and your total first stage gain can be huge.
Second stage gain is Rout at M5 * gm of M5. Since this transistor is big (5000/1 maybe?) this stage gm will be high, but Rout will be low. Gain2 = gm(M5) * (Rout(M5) || 2.5k || R6). Probably pretty low, but we get miller multiplication of the cap by this second stage gain so it is nice here.
Now to compensate the amp, I would add an AC source in the base path between R2/R3 and the npn's. Call the resistor side of the AC source XX and the npn side YY. Sweep from 1Hz to 100MHz and plot db(V(XX)/V(YY)) and p(V(XX)/V(YY)) to get gain and phase.
NOTE: I think its V(XX)/V(YY) but I may be wrong. If you get a gain of -50dB that rises instead of falls, I have it backwards, use V(YY)/V(XX). You should get +50dB (or more) that falls at a pole given by C1*Gain2 * (Rout(M5)||R6||2.5k)
Increase C1 until you get about 50-55 degrees phase margin at the 0-dB point.
Now for some fun. Add a resistor in series with C1 of value 1/gm(M5) to give you a zero to cancel the frequency shift of the second stage. Now I bet you have more than 90 degrees phase margin at the crossover and this circuit will be rock solid.
Now as far as your glitch is concerned, let me explain why an output cap is needed. I see you are using a 2.5k as the shunt resistor. For an output voltage of 2.5v, this means 1mA is flowing through M5. This will require a big device which is slow, making glitches unavoidable without an output cap. A 25k will be more forgiving, and will need a smaller output cap.
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