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bandgap voltage reference

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dragonslayer

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I would like to ask a question. For bandgap voltage reference, how do you use a capacitor to make this designed voltage insensitive to supply voltage variations. The design that I have done, the capacitor that I need to minimize glitch is 0.1micro and it is too big. If i put 1n, this cap has no effect. Is there somehting wrong with the design? How does this capacitor work actually?
The 2nd question is what is the reverse breakdown voltage and reverse dynamic impedance of a bandgap voltage?
Thank you very much. Any help on this is greatly appreciated.
 

penghan

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Place 3 Capacitor in parallel(Those capacitor's value are of two or three order difference in sequerence).
 

Fom

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Do you use an OpAmp and Miller capacitor for it's frequency compensation? If so it can make your bandgap to be sensitive to VDD noise. But it depends on circuit configuration.
 

survivor

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You may include a small regulator inside the Bandgap ckt to boost the PSRR+ of the reference voltage. As for PSRR-, the only way i know is to add more decoupling cap on the reference voltgae signal.
But that will slow down the response time of the reference voltage. SO you must trade-off based on your application.
 

Question

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You can use MOS as capacitor. Add some capacitors between bandgap output and VSS.
 

dragonslayer

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The file attached shows the capacitor i am talking about.
What do you guys think the capacitor is there for and how does it affect the circuit?
i was thinking that it is to compensate (frequency) but i am not sure
does anyone have a clue?
 
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dragonslayer

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Question said:
You can use MOS as capacitor. Add some capacitors between bandgap output and VSS.

how do i do this?
 

electronrancher

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dragonslayer - this is a quite brilliant circuit, where did it come from? i would like to buy the book, or to get a copy of the class notes where this occurrs. can you PM me?

in exchange I will solve your problem. this circuit is a very clever implementation of a shunt bandgap reference. It gives an output voltage (at top of R2) of R2/R1*Vbg. In essence, it acts as a bandgap comparator where M1/M6 are the amplifier output and M5 is a big power device, shunting away current until voltage at the base of the npn is Vbg.

To answer your question, C1 is only used to compensate the amplifier to a dominant pole, not really to avoid output glitches. If you look at shunt references in general on Maxim or TI website, they usually have 1uf-10uf in parallel to R6 - this large capacitance is what is used to avoid output glitches. The internal capacitor C1 is used to compensate the amp, probably less than 10pf.

Let's assume the reference is in regulation. A bias current determined by the deltaVbe/R4 should be running through Q1, Q2, M2, M3 and therefore M1/M6 also. Using this current you can find the Rout of the M1/M6 pair.
Now since the master current is steered by Q1/Q2, we can say the gm of this amp is Ie(Q1)/kT/q or roughly Ic /.0259,

Gain of this first stage would be Gain1 = gm(q1) * Rout(M1) || Rout(M6). This gain can be increased by making M1 & M4 a multiple of M2/M3, which increases gm to k*gm where k means M1 is k times bigger than M2. In this manner, the M1/M6 amp can be given very big current gain. Make these transistors long or cascode them to give big Rout, and your total first stage gain can be huge.

Second stage gain is Rout at M5 * gm of M5. Since this transistor is big (5000/1 maybe?) this stage gm will be high, but Rout will be low. Gain2 = gm(M5) * (Rout(M5) || 2.5k || R6). Probably pretty low, but we get miller multiplication of the cap by this second stage gain so it is nice here.

Now to compensate the amp, I would add an AC source in the base path between R2/R3 and the npn's. Call the resistor side of the AC source XX and the npn side YY. Sweep from 1Hz to 100MHz and plot db(V(XX)/V(YY)) and p(V(XX)/V(YY)) to get gain and phase.

NOTE: I think its V(XX)/V(YY) but I may be wrong. If you get a gain of -50dB that rises instead of falls, I have it backwards, use V(YY)/V(XX). You should get +50dB (or more) that falls at a pole given by C1*Gain2 * (Rout(M5)||R6||2.5k)

Increase C1 until you get about 50-55 degrees phase margin at the 0-dB point.

Now for some fun. Add a resistor in series with C1 of value 1/gm(M5) to give you a zero to cancel the frequency shift of the second stage. Now I bet you have more than 90 degrees phase margin at the crossover and this circuit will be rock solid.



Now as far as your glitch is concerned, let me explain why an output cap is needed. I see you are using a 2.5k as the shunt resistor. For an output voltage of 2.5v, this means 1mA is flowing through M5. This will require a big device which is slow, making glitches unavoidable without an output cap. A 25k will be more forgiving, and will need a smaller output cap.
 

dragonslayer

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i must say your explaination is very detailed !
i will try out what you said to see if i can get the results
check you pm!
electronrancher said:
dragonslayer - this is a quite brilliant circuit, where did it come from? i would like to buy the book, or to get a copy of the class notes where this occurrs. can you PM me?

in exchange I will solve your problem. this circuit is a very clever implementation of a shunt bandgap reference. It gives an output voltage (at top of R2) of R2/R1*Vbg. In essence, it acts as a bandgap comparator where M1/M6 are the amplifier output and M5 is a big power device, shunting away current until voltage at the base of the npn is Vbg.

To answer your question, C1 is only used to compensate the amplifier to a dominant pole, not really to avoid output glitches. If you look at shunt references in general on Maxim or TI website, they usually have 1uf-10uf in parallel to R6 - this large capacitance is what is used to avoid output glitches. The internal capacitor C1 is used to compensate the amp, probably less than 10pf.

Let's assume the reference is in regulation. A bias current determined by the deltaVbe/R4 should be running through Q1, Q2, M2, M3 and therefore M1/M6 also. Using this current you can find the Rout of the M1/M6 pair.
Now since the master current is steered by Q1/Q2, we can say the gm of this amp is Ie(Q1)/kT/q or roughly Ic /.0259,

Gain of this first stage would be Gain1 = gm(q1) * Rout(M1) || Rout(M6). This gain can be increased by making M1 & M4 a multiple of M2/M3, which increases gm to k*gm where k means M1 is k times bigger than M2. In this manner, the M1/M6 amp can be given very big current gain. Make these transistors long or cascode them to give big Rout, and your total first stage gain can be huge.

Second stage gain is Rout at M5 * gm of M5. Since this transistor is big (5000/1 maybe?) this stage gm will be high, but Rout will be low. Gain2 = gm(M5) * (Rout(M5) || 2.5k || R6). Probably pretty low, but we get miller multiplication of the cap by this second stage gain so it is nice here.

Now to compensate the amp, I would add an AC source in the base path between R2/R3 and the npn's. Call the resistor side of the AC source XX and the npn side YY. Sweep from 1Hz to 100MHz and plot db(V(XX)/V(YY)) and p(V(XX)/V(YY)) to get gain and phase.

NOTE: I think its V(XX)/V(YY) but I may be wrong. If you get a gain of -50dB that rises instead of falls, I have it backwards, use V(YY)/V(XX). You should get +50dB (or more) that falls at a pole given by C1*Gain2 * (Rout(M5)||R6||2.5k)

Increase C1 until you get about 50-55 degrees phase margin at the 0-dB point.

Now for some fun. Add a resistor in series with C1 of value 1/gm(M5) to give you a zero to cancel the frequency shift of the second stage. Now I bet you have more than 90 degrees phase margin at the crossover and this circuit will be rock solid.



Now as far as your glitch is concerned, let me explain why an output cap is needed. I see you are using a 2.5k as the shunt resistor. For an output voltage of 2.5v, this means 1mA is flowing through M5. This will require a big device which is slow, making glitches unavoidable without an output cap. A 25k will be more forgiving, and will need a smaller output cap.
 

Fom

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Circuit is very interesting, but it is impossible imlement that in pure digital CMOS process, because there are no such kind of bipolar transistor. For digital CMOS the only BJT is parasitic transistor to substrate. So collectors of these transistors should be connected to the most positive voltage (VDD) if N-type substrate is used. For P-type substrate only PNP transistor with collector connected to the most negative voltage (or GND) can be used.
 

JPR

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It seems to me that C1 and any filter capacitance added are in conflict. There are two primary poles to this circuit, one at the drain of M5 and one at the gate of M5. Placing large (uF) capacitance at output will make the pole at drain of M5 slow (assuming R1 is dominant with 1uF capacitor will make the pole at 64Hz, this could be as high as 125Hz with load at 1mA). Adding the capacitor C1 also makes pole at gate of M5 low frequency. Unless C1 is VERY large, the pole at the gate of M5 is probably between 1mHz and 10Hz, which is close to the pole at the drain of M5, leaving very little phase margin.

If there is no output cap, the node at the drain of M5 will be higher frequency, and phase margin will be good, but glitches would occur with transients of current. The same will hold if C1 is made larger or current is removed from M1/M6 to reduce the frequency at the gate of M5 to make it more dominant.

Addition of a series resistance with C1 will help to alleviate some of this. However, for the zero to be effective, it would need to cancel out the pole at the output (remember that the pole will be between 64Hz and 125Hz with a 1uF output capacitor), so the resistance would need to be very large (hundreds of Megohms?), so would need to be created by a properly biased active device. With the associated zero being at such low frequency, I find very little benefit from C1 if a large load capacitor is used, or am I missing something in my analysis of the circuit.

It seems more likely to me that the cirucit (with C1 included) is indended to NOT have a large filter capacitor at the output, and will be limited to use where fast current transitions DO NOT occur.
 

electronrancher

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think about it this way - compensate the circuit for single pole rolloff. now box the whole circuit up in a little symbol, and define the ac characteristics of this little symbol as a single pole rolloff.

now why couldn't you add an rc to this? let's think about it. It will give a low-frequency pole, and if this new low-frequency pole is too close to your internal pole, you will have an unstable circuit.

So what can you do? You can add a resistor in series with this new output cap in order to create a zero, OR - you can use a cheap electrolytic cap which already comes with a parasitic ESR zero.

Ta-daa! Go look at datasheets for shunt regulators, they almost always have a graph of "STABLE REGION VS OUTPUT CAP" that shows a wide strip of stability in the 1uf-10uf range, then instability above and below this. For a given current into M5, it's easy to calculate the Rout*C for the output cap pole, and find if you are getting into trouble.

Cap manufacturers usually list their ESR in datasheets, or you can use an estimate from Abraham Pressman's book on power supply design where Resr*C = 65e-6. It's just an estimate, but for a 6.5uf cap you can expect an ESR of 1Ohm and so forth.
 

JPR

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electronrancher:

I understand the reason to make the circuit act with a single pole rolloff, however, I do not see the single pole rolloff in the given circuit WITH a uF range output capacitor!

It appears to me that you would get a 2-pole rolloff for much of the gain, which would leave almost no phase margin!

Let me take an example, and you can tell me where I am going wrong...

Lets take gm of M5 to be 10millimhos, and current in all other transistors to be 1uA each. Let use 10pF for C1 and 6.5uF for output capacitor. gm of Q1 and Q2 will be something around 40umhos. Rout of M1/M6 will be something around 25megohms. Gain of first stage will then be 1000. If gm of M5 is 10millimhos, gain at output will be 25. Total gain is 25k = 88dB. Pole at drain of M5 will be about 10Hz. Pole at gate of M5 will be about 25Hz. The zero due to the 10 ohm ESR on the 6.5uF cap will be at 2.5kHz.

Open loop gain will be 88dB out to 10Hz, where rolloff will start at -20dB/decade out to 25Hz (down to 80dB), where rolloff will become -40dB/decade. 0dB will be reached at 2 decades out, which will be 2500Hz.

Now, looking at the phase. The phase change will be 180 degrees (negative feedback) at DC. This will start dropping at 45deg/decade at 1Hz, and will change to 90deg/decade at 2.5Hz. At 100Hz the phase will level back out to 45 deg/decade. At 250Hz, the phase will be VERY CLOSE to zero. The phase change from the two poles will be about 90deg each, and the phase improvement from the zero will be just starting. Anything else in the circuit that might tend to decrease the phase will now cause positive feedback with some gain, and the circuit will tend to oscillate.

If C1 is made larger, there will be a larger region of zero phase margin before the phase starts to improve. If C1 is made smaller, the minimum phase will be increased. The phase margin will reach 90 degrees when the pole at the gate of M5 is equal to the zero from the ESR. However, reducing C1 to zero might not not even reach this point, since, as you pointed out in another reply, M5 is very large, and will have a large capacitance. This is why, it seems to me, that C1 is hurting rather than helping the circuit if a large filter capacitor is used, and why, I believe, the circuit with C1 included is intended to be used without a filter capacitor.

If the current in all devices except M5 is changed, there will be a point where the pole at the gate of M5 will be equal to the zero on the output capacitor. Beyond this point, C1 could be used to compensate. However, it seems to me that the same compensation that C1 creates could be achieved by keeping the currents such that the pole at the gate of M5 is at ideal WITHOUT needing C1?

Is there some additional benefit for having C1 in place? (As dragonslayer originally asked.)
 

JPR

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electronrancher:

To simplify:

I understand how C1 will help stability if there is NO large capacitance on the output, but please help me to understand how C1 helps the circuit stability when there is?
 

JPR

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I also made a mistake in determining the ESR zero. I misread 1 Ohm to be 10 Ohm in your post. 1 Ohm will put the zero out at 25kHz, which will be at 2x the closed-loop-bandwidth in the example I gave. This will lead to no improvement in phase in the example, since the phase shift from the zero will be just starting at the point of 0dB gain!

To make the circuit have good phase margin, the 2nd pole would have to be moved from 25Hz to the 25kHz to match up with the ESR zero, which would necessitate increasing the frequency at the gate of M5, rather than reducing it (which the miller-multiplied C1 would do!)

If the pole at the gate of M5 is to be the dominant pole, it would need to be at an even lower frequency (leading to a very large capacitance for C1, even with miller effect!), and would need a low frequency zero (at 10Hz) to compensate for the 2nd pole. To achieve this low frequency pole, a resistance MUCH higher than the 1/gm(M5) that you quoted earlier would be needed!

Add on top of this the fact that the gm of M5 (and thus, open loop gain) will change with load current, and compensation of such a circuit is far from trivial.
 

JPR

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I further analyzed the circuit, and realized why C1 should not hurt results. The gain in the first stage is MUCH lower than I originally thought. The current gain (Gmtot) will be GmeffQ1-GmeffQ2, since both bases are tied to the same input. GmeffQ1 will be 1/(1/GmQ1+R5) and GmeffQ2 will be 1/(1/GmQ2+R4+R5).

With the output in regulation, GmQ1 = GmQ2 = I/Vtherm. R4 will be Vtherm*ln(ratio)/I, where ratio is the ratio of emitter sizes between Q1 and Q2, and R5 will be approximately 0.6/(2*I) (so that the voltage drop across R5, plus vbe will be equal to the bandgap voltage of approximately 1.2V.

With this, Gmtot will be (Vtherm*I)/[(0.3+Vtherm)*(0.3+Vtherm+Vtherm*ln(ratio)].

With I = 1uA and ratio = 5, this will be 0.211umhos (rather than 40umhos). If I = 10uA and ratio = 25, Gmtot will be 1.9umhos (rather than 400umhos). As you can see, this will dramatically reduce the total loop gain (by a factor of about 200x or 45dB. This means that the original gain of 88dB would be dropped to about 43dB, and it would be difficult to hit zero phase margin with a two pole system, unless the two poles were almost on top of each other!

What this means is that the circuit will be much easier to compensate, so placing a high value capacitor at the output, along with C1 will probably be okay (just need to keep the two poles from being the same), but the output resistance will be higher than with a high gain system.
 

mady79

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I think C1 is for internal compensation and large ouput load of 1u to 10u F is for external capacitor .But I think by properly desiging for Rout (M1,M6) (preferably low value so as to make gate of M5 as the non dominant pole ) one could avoid this internal compensation and just do the external compensation to avoid the glitches due to clock feedthrough and get better Phase margin as well .May be we can still live with external compensation .
 

electronrancher

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OK JPR, I agree that the amp is in the 40-50db range and not the 80-90dB range. It still seems that if you make the compensation cap into a zero you can get away with the high gain configuration as now you assume this second pole (comp cap) gives no overall phase shift.

zeroes save lives! i love them.
 

electronrancher

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ps - from sim, mady is right, you can compensate externally and this guy is OK. but that's not how it's done since your circuit MAY not be stable if the user's condition is not right. hoping is a no-no, and murphy's law says your mistake will be found by customer! ;)
 

JPR

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electronrancher:

I do not disagree that the zero can help in the case of a high gain circuit. However, for this to be the case, the zero MUST be at a frequency where it can impact the phase before the closed-loop bandwidth.

If C1 is used, the zero from the ESR on the output cap will be out too far to help, so you must rely on the zero from the addition of an impedance (real resistance, 1/gds, or 1/gm) in line with C0 which will add a zero. To maintain a perfect 1-pole roll off, the zero needs to line up with the pole at the output. If the ouptut uses a 6.5uF cap, the zero will need to be at approximately 10Hz to perfectly counteract the output pole.

This is why I originally suggested (thinking that this WAS a high gain scenario) that the circuit, with C1 included, was "intended to NOT have a large filter capacitor at the output, and will be limited to use where fast current transitions DO NOT occur."

Additionally, keep in mind that, with the addition of a zero via series resistance, there will be an added pole at some higher frequency, which will be at roughly the same frequency as the node without the capacitance added. If your bandwidth is high enough, these poles can contribute phase shift (or even gain attenuation) at the closed-loop bandwidth of the circuit! This would be especially the case for the gate of M5, where the large capacitance of M5, combined with the high output resistance of the previous stage, will produce a pole that can easily be within the bandwidth.

(The same could hold true for the output if a ceramic capacitor was also added, such as to suppress glitches that could be present if the output pole was not the lowest frequency pole in the system..)
 

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