Indeed, the absolute value of the current (determined by R1) will influence the bandgap output voltage. But it's a second order effect. If the resistance changes +/- 10% (typical for IC processes), the output voltage will only change +/- ln(1.1)*Vt = +/- 2.5 mV.
However the spread of Is and Beta in the transistors will give more deviation.
Haha - you guys need to start doing your maths on this stuff.. For the most part, it washes out. For example: Multiply all resistors by 1.2. now ptat current is 20% less than you previously thought, but Rgain is 120% of what you previously thought => 1.
In reality, we add trim circuits to bandgaps once we start worrying about process variation. BUT - for a "draw it and go" bandgap, you should be able to get within a few percent without trim.
Question on the bandgap circuit:
What threshold voltage have the NMOS transistors ?
NMOS gate-sourse voltage should be less than voltage of diodes over temperature range !
In reality, we add trim circuits to bandgaps once we start worrying about process variation. BUT - for a "draw it and go" bandgap, you should be able to get within a few percent without trim.
This bandgap circuit is constructed in voltage mode and the resistor does affect the temp coefficient of the bandgap circuit as it is temperature dependent too. Such problem can be cancelled out if current mode bandgap is used.
it also should be concerned that the load of the Vref will affect the banggap, if the Ip-p of the load is 4ua, how to get the right quisient current in the output stage of the bandgap?
In this circuit, there is the start-up circuit at the right. Anyone can discuss how the start-up circuit works in this bandgap circuit? And is there a power-down circuit? If no power-down circuit, how to simulate the start-up circuit?
In your bandgap equation, K= R2/R1 * ln where n is the ratio between bipolar. So your are independant of resistor variation in case of you've matched your resistor in the layout.
Startup circuit will work:
Initially R3 will pull down gate of M6 so M6 is off. So Gate of M5 will high turning on M5. This will pull down gate of M1,M2 ,M3 so all current sources starts flowing current so bandgap will start. Once Vref will come up and circuit is self sustaining.
M6 is On which is much sttronger then upper diode connected P tranistor so M6 On , switching off M5.
Power down signal will be added up to diode connected P transistor. Instead of making it diode connected , gate of it will be connetced to powerdown.