Band gap stability analysis

[subhash_chevella]

Hi All,

Generally, in Band-gap references we do insert a small "ac signal" in between output of Op-Amp & gate terminals of PMOS transistors, for analyzing stability, right?

As we know, output of Op-Amp is the low impedance node.
What ever the small ac signal we are applying will go into the output of Op-Amp as it is low impedance node. What ever the signal we apply has to pass through the loop for analysis purpose, which is not happening in this case, right? Then how can we analyze the stability?

Could any one help me in understanding this? Am I missing anything?

Thank you.

regards,
Subhash C

 

[erikl]

As we know, output of Op-Amp is the low impedance node.

Right. Consider it as a DC voltage source. You then add an ac voltage source in series, which simply adds DC+ac. This ensures the correct DC feedBack, i.e. preservation of the right operation point.

 

[D.A.(Tony)Stewart]

Stability is usually analyzed with unity gain step response or open loop gain-phase or closed loop gain-phase.

Which case did you have in mind?

 

[SIDDHARTHA HAZRA]

Generally, in Band-gap references we do insert a small "ac signal" in between output of Op-Amp & gate terminals of PMOS transistors, for analyzing stability, right?

As we know, output of Op-Amp is the low impedance node.
What ever the small ac signal we are applying will go into the output of Op-Amp as it is low impedance node. What ever the signal we apply has to pass through the loop for analysis purpose, which is not happening in this case, right? Then how can we analyze the stability?

Could any one help me in understanding this? Am I missing anything?

It would be good if you can post a snapshot of the op-amp architecture and bandgap. It would help us to analyze your point. More over in bandgap we generally do not go for a op-amp but an OTA which is used as an error amplifier to maintain a constant voltage at both of its inputs and hence the bandgap output .

 

[FvM]

I must confess, I don't understand the problem addressed in your post. Having a low impedance node at one side of the test voltage source (and a high impedance node at the other) is in fact a prerequisite for simple loop gain calculation.

A complete analysis of the loop gain measurement problem can be found in the classical Middlebrook paper, quoted in this thread: https://www.edaboard.com/threads/300916/
More related contributions are here https://www.edaboard.com/threads/177993/

P.S.: I noticed that the first document location isn't available any more. You need to find another source for R.D. Middlebrook, Measurement of loop gain in feedback systems.

 

[erikl]

P.S.: I noticed that the first document location isn't available any more.
You need to find another source for R.D. Middlebrook, Measurement of loop gain in feedback systems.

Thanks to Franks former link, I saved it at that time. Here it is: View attachment MiddleBrook75.pdf