Sink+Source Refence Current Generator Stability

[celebrevida]

I have designed the following Isource and Isink current reference generator with Isource=Isink on purpose.

When I simulate this circuit in DC, it works. SPICE will find the final steady state solution that I seek.

But in TRAN, the circuit is unstable and the two opamps fight each other forever.

Is there a way to get this circuit to stabilize? I tried many different values of the RC miller feedback for each opamp but it doesn't work.

(I could of course break the circuit up into two indepence Isource and Isink references but the whole purpose is to ensure Isource=Isink)

Thanks for any insight and help!

 

[KlausST]

Hi,

I guess you just need one capacitor or RC at one variable_resistor_end to GND to prevent the circuit form oscillating.

If you expect to give some recommendations for the values, you need to give your design values first.

Klaus

 

[celebrevida]

Hi,

I guess you just need one capacitor or RC at one variable_resistor_end to GND to prevent the circuit form oscillating.

If you expect to give some recommendations for the values, you need to give your design values first.

Klaus

Thanks for your response. Rbias=323k, Ibias=275nA if that helps.

One thing I noticed is that the RC miller compensation for each opamp was making things worst. Removing both of them helped a great deal such that the oscillations reduced considerably to the point that they die out eventually after a long time.

But I am now stuck again as I can't figure out how to improve it from here.

 

[KlausST]

Hi,

I just recognized that this is an IC design.
--> please post in the IC design forum section.

I´m not an IC designer.

Klaus

 

[dick_freebird]

Far better to accept some open loop error than to put two rats in a cage.

Look to CMFB schemes. One amp fast, one amp slow. Pick a winner beforehand. Use one amp to set the "prime" current and another to make the other, track - but "know it's place".

 

[D.A.(Tony)Stewart]

Your loop has PI feedback with no margin. Changing the pole only shifts the oscillation.

I believe it is not a linear oscillation, but rather a non-linear Relaxation Oscillator.

@KlausST This is a control system's problem before it ever gets integrated.

What are Vt, Beta of each FET?

This makes a good relaxation oscillator due to the Miller capacitance (pF) in either FET.

--- Updated Mar 20, 2025 ---

Reducing the gain to either or both OA's from 100k to 10 would not stop the Relaxation Oscillator for me. One FET is "Off" while the other is hunting.
Removing both Miller C's makes it stable or all Ciss, Coss.

So it seems two rats or even one mouse or kangeroo with Miller or load capacitance forces one gate off while the other integrates then the other flip hops.

--- Updated Mar 20, 2025 ---

Similar efforts have tried without success recorded. https://www.edaboard.com/threads/loopgain-analysis-with-multiple-feedback-loop.388393/

RG site paper suggests this .

TL;DR https://www.researchgate.net/publication/224347132_Compact_class_AB_CMOS_current_mirror/figures?lo=1


I did not see any description of the problem issues due to Off/On oscillations.

Just a theoretical analysis without all the necessary control theory.

 

[celebrevida]

The variable resistor is meant to be 363k. Thus the Ibias=245nA.

Interestingly, removing the two RC feedback seem to help somewhat in the sense that while the oscillations are there, they do eventually die out.

 

[D.A.(Tony)Stewart]

yes all time lag in the loop aggrevates the hysteresis effects of either FET shutting off.

I think the ultimate solution will be to "linearize" the design.

This means to prevent gate cutoff on both error amplifiers.

But with Vt tolerances being what they are makes Vgs {min:max} a difficult choice if not impossible
Considering Vt max/min ratios are ~2:1. The Vout minimum, must be greater than Vt at a current lower than your setpoint. But how can this process be controlled by design (?)

--- Updated Mar 20, 2025 ---

Upon reflection, I think using NFB on each FET can prevent the off state with appropriate R values for Rdg and Rg to error amp.

 

[celebrevida]

Removing the Miller RC feedback for both opamps helped.

By removing them from both opamps, the circuit stability is still not great but the oscillations do die out after a few microseconds rather than go on forever.
(I am guessing that these were adding or pushing 2-poles at low frequency. Not an issue with a single opamp but could see why it doesn't work with two opamps).

Examining the circuit further, I saw the possibility of a "feed-forward" path to help stability.

By adding a cap between biasp and vbot, call it Cff, I create a situation where, for example:
opamp_biasp pushes down biasp which pulls up vtop up to 0.45V
falling biasp pushes down on vbot through Cff, below 0.35V (and counteracts vbot being pulled up through Rbias, if Cff wasn't there)
opamp_biasn then tries to drive vbot back to 0.35V
In this case, both opamps aren't fighting directly. As you can see they can work together more or less to drive vtop and vbot to the desired voltages.

But without Cff, you have a situation where:
opamp_biasp pulls up vtop also pulls up vbot through Rbias
opamp_biasn then sees this and tries to push vbot down which pushes vtop down
opamp_biasp then sees this and tries to pull vtop up which pulls vbot up
repeat forever

Not sure if mathematically in transfer function analysis if Cff is considered shunt feedback or feedfoward feedback. I am guessing it is adding a zero.

All I know is that adding Cff with the optimal value, the oscillations die down in < 100ns instead of several microseconds.

(I also tried putting in Cff between vtop and biasn instead as that should also work and indeed it does. Putting in two Cffs though doesn't work but it's easy to see why as that just results in a situation that is the same as having no Cff).

 

[D.A.(Tony)Stewart]

It is the classic Astable Multivibrator (Relaxation Oscillator) which uses the off states thus "nonlinear active devices" with positive feedback with delays.

Poles and zeros are not useful mathematical terms in this case. If so then adding D functionality to a PID compensation loop could solve the problem. This is why I suggested converting to a linear control system, but I have no solid evidence or solution yet. Nonlinear systems like this have no gain when the loop is opened and the FET is in the OFF state.

This is why Dick suggested a sequential fast regulator 1st then a slow regulator 2nd.
The trick is to not let the 2nd regulator disturb the 1st regulator as it over-reacts to overshoot and cuts off.
Perhaps changing BW like a fast acquire loop that slows after error is near zero, like some PLLs and Lock-in amplifiers I have built.