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how to simulate open loop gain with hspice

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tailbit

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I am new to analog world, can someone show me how to set up and write the hspice input file to simulate the open loop gain/phase margin for this single stage OP Amp? It's an OP amp with negative feedback.
Many thanks
 

The technique I use is to connect it in non-inverting configuration with an AC source on the non-inverting input. Put a very large resistor between the output and inverting input (e.g. 1G ohm). Add a very large capacitor (say 1Farad) from the inverting input to ground. The characteristic you will then get is the open loop gain & phase.

Keith.
 
Since TAILBIT is pretty "new to the analog world", we should mention that he should not expect to see the opamp dc gain as a result of this simulation.
Instead, there will be lower corner frequency in the region of 1/(2*Pi*R*C). In fact, that's the reason for the large values.
 

LvW said:
Since TAILBIT is pretty "new to the analog world", we should mention that he should not expect to see the opamp dc gain as a result of this simulation.
Instead, there will be lower corner frequency in the region of 1/(2*Pi*R*C). In fact, that's the reason for the large values.
Click to expand...

Correct. Sorry I neglected to say that.

I think there are analysis modules you can put around functional blocks in some simulation software (e.g. Cadence) to achieve a similar result, but they vary from simulator to simulator.

Keith.
 

That's exactly what I have seen on the low frequency. I have seen people cut the negative feedback then supply the DC + small AC to the non-inverting input and supply same DC on the inverting input for AC simulation. What is the difference between this technique vs. big RC feedback technique? are they suppose to be the same?
 

The benefit of using a single voltage source and large capacitors/resistors is that you don't get problems with amplification of the opamp offsets. I think that unless you are careful with using dual DC voltage sources you will amplify the opamp offset by the open loop gain of the opamp. Then its output will saturate and the measurements will be useless. While you can introduce a small offset in the DC voltage sources to compensate, the value required will change with temperature and the actual design. If you change transistor sizes to tweak the design you would then need to alter the DC voltages to follow the offset if it changes.

The disadvantage of the large capacitor/resistor method is the values of the components can affect the results, particularly with bipolar designs where you cannot use 1G ohm as you need to supply the input bias current. Low feedback resistor values can give a false open loop gain as they will load the output stage. I still use that method with bipolar - you just have to be careful.

Keith.
 
The disadvantage of the large capacitor/resistor method is the values of the components can affect the results
Click to expand...
The same way, you can use ideal passive components of any value in simulation setup, you can also use ideal buffers respectively controlled
sources to get rid of the said problems. Creative thinking is required, however.
 

Based on your suggested RC low-pass inverted feedback: Adding an ideal buffer removes any input current problems.
 

Here is another simulation arrangement down to (nearly) dc and without any loading errors (see pdf attachement).
 
LvW said:
Here is another simulation arrangement down to (nearly) dc and without any loading errors (see pdf attachement).
Click to expand...

Thanks, that's useful. I must admit I have tended to use large R/C but it has its limitations.

Keith.
 

Yes, very often I use this principle (ac voltage source in series with the feedback loop) - without the ideal buffer - also for loop gain simulation. In this case, the ac source must be placed with one of its nodes either at the low resistance opamp output or in front of a high resistance opamp input.
Thus, it is a simplified version of Middlebrook's errorless method (using a current source for a second simulation run). As a consequence of the simplification, there is a small error for very high frequencies, when the neglected input resp. output impedances come into play.
 

Thanks for all the feedback, I think the discussion has gone beyond my level of underatanding. I have attached 2 configuration for open loop simulation that I am currently using, can anyone help me explain which way is right and which way is better and what is the right hspice statement to use for Vdb , and Vp?
Thanks in advance!
 

Sample_2 with DC bias will work. The other circuit would only work if you got the DC voltages exactly right so the output was in its working range which is tricky.

Keith
 

    T

    tailbit

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Thank you Keith!
I have another question about the AC signal input in HSPICE. Here is my DC and AC input
VXX pot1 port2 DC 1V AC 1, this AC 1 is it really necessary to be "1", or it can be any voltge? how about AC 0.1? what is the difference?
When specify the plot in HSPICE,
PLOT AC VDB(output) or VBD(ouput, DC+AC input signal)? In the HSPICE manual, it says the first one is output with respect to GND, and 2nd one if output with respect to the input.
 

You can use 'AC 0.1' but then the output numbers will be confusing. Using 'AC 1' means the output will plot correctly in dB as gain, or if you plot is in volts it will be 'volts out per volt in' (but not a 'real' volt in - you cannot have 1000V out of your opamp!).

I would say you want VdB(output). I am not sure what the second form would actually do. The DC component shouldn't affect the calculation so it may produce the same result. My Spice isn't Hspice so there may be syntax differences.

Keith

Added after 1 hours 15 minutes:

By the way, the form Vdb(out,in) is normally used when you want to probe interstage gain. For example, if you had a two stage amplifier so INPUT, OUT1, OUT2 - you could probe OUT2 and OUT1 easily enough, but if you wanted to know what the second stage contributed to the output you would plot Vdb(OUT2, OUT1). It plots OUT2/OUT1 in log form.

Keith.
 

Keith, thank you for the explanation that helps a lot.
 

Hey, Keith
As you mentioned earlier 1F + 1G ohm between output and feedback node, how small and how big these 2 elements (R, and C) can be? is there a limit ?
Thanks
 

I am not sure. If the resistor is too high you will eventually get leakage problems affecting the bias. Other than that it is probably just a case of when the maths routines in the simulator run out of range, but the range is pretty large.

Keith.
 

As said before, the analyzer would prefer ideal circuit elements like voltage buffers, or calculating the loop gain from a voltage ratio, as
LvW suggested. Using artificial high RC products for biasing networks is possibly nearer to intuitive circuit understanding. 1G isn't actually
a high resistance, but you can refer to the node resistance accuracy limits specified in the transient analysis solver options. As long as you
don't get DC operation point convergence problems, it's most likely O.K.
 

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