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ajrox

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Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity txbuffer is
    Port ( init,cs,rst,write : in std_logic;
           data_in : in std_logic_vector(7 downto 0);
           clk,w_clk : in std_logic;
           busy,frame_done : out std_logic;
           bit_out : out std_logic);
end txbuffer;

architecture Behavioral of txbuffer is
function crc_calc(CRC1 : std_logic_vector(15 downto 0))	  --function to calculate crc
  return std_logic_vector is
  variable result : std_logic_vector(15 downto 0);
  begin
   result := CRC1;
	for i in 0 to 7 loop
	 result := '0' & result(15 downto 1);
	  if(result(0)='1') then
	   result := result xor x"A001";
	  end if;
	end loop;
  return result;
end crc_calc;

type mem is array(0 to 255) of std_logic_vector(10 downto 0);					
signal buffer1 : mem ;
signal count : integer range 0 to 255 :=0;
signal byte_count : integer range 0 to 255 :=0;
signal bit_count : integer range 0 to 15 :=0;
signal finalCRC : std_logic_vector(15 downto 0);
signal crc_send : BIT :='0';
begin
process(init,rst,cs,write,w_clk)
 variable CRC : std_logic_vector(15 downto 0) :=x"FFFF";
 variable data : std_logic_vector(7 downto 0);
begin
 if(init ='1') then
  busy <='0';
  CRC := x"FFFF";
  count <= 0;
  frame_done <= '0';
  bit_count <= 0;
  crc_send <= '0';
 elsif(cs='1' and cs'event) then
  busy <= '1';
  data := data_in;
  CRC(7 downto 0) := CRC(7 downto 0) xor data;
  CRC(15 downto 8) := CRC(15 downto 8);
  CRC :=crc_calc(CRC);
  buffer1(count)(10) <= '1';
  buffer1(count)(0) <= '1';
  buffer1(count)(9) <= not(data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0));
  buffer1(count)(8 downto 1) <= data;
  count <= count + 1;
 elsif(rst='1') then
  finalCRC <= CRC;
  CRC := x"FFFF";
  byte_count <= count;
  bit_count <= 0;
  count <= 0;
  busy <= '0';
  frame_done <='1';
  crc_send <= '0';
 elsif(write='1' and w_clk='1' and w_clk'event and crc_send ='0') then
  bit_out <= buffer1(count)(bit_count);
  bit_count <= bit_count + 1;
  if(bit_count > 10) then
   count <= count + 1;
	bit_count <= 0;
  else
   null;
  end if;
  if(count > byte_count) then
   crc_send <='1';
	count <=0;
	bit_count <= 0;
  end if;
 elsif(write='1' and w_clk='1' and w_clk'event and crc_send ='1') then
  bit_out <= finalCRC(bit_count);
  bit_count <= bit_count + 1;
  if(bit_count > 15) then
   crc_send <= '0';
  end if; 
 end if;
end process;

end Behavioral;

The above vhdl code is giving many signals as non-synthesizable-CRC,busy,count.
Can some one please help me?
Also can anyone suggest me some guidelines for synthesizble coding for vhdl
 

Try this and check if it works:

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY txbuffer IS
    PORT ( init,
           cs,
           rst,
           write        : IN std_logic;
           data_in      : IN std_logic_vector(7 DOWNTO 0);
           clk,w_clk    : IN std_logic;
           busy,
           frame_done   : OUT std_logic;
           bit_out      : OUT std_logic
         );
END txbuffer;


ARCHITECTURE Behavioral OF txbuffer IS

function crc_calc(CRC1 : std_logic_vector(15 DOWNTO 0))   --function to calculate crc
  return std_logic_vector IS
  variable result : std_logic_vector(15 DOWNTO 0);
  BEGIN
   result := CRC1;
        for i IN 0 TO 7 loop
         result := '0' & result(15 DOWNTO 1);
          IF(result(0)='1') THEN
           result := result xor x"A001";
          END IF;
        END loop;
  return result;
END crc_calc;

TYPE mem IS array(0 TO 255) OF std_logic_vector(10 DOWNTO 0);

SIGNAl buffer1     : mem ;
SIGNAL count       : INTEGER RANGE 0 TO 255  :=0;
SIGNAL byte_count  : INTEGER RANGE 0 TO 255  :=0;
SIGNAL bit_count   : INTEGER RANGE 0 TO 15   :=0;
SIGNAL finalCRC    : std_logic_vector(15 DOWNTO 0);
SIGNAL crc_send    : BIT :='0';


BEGIN

PROCESS( init, rst, cs, write, w_clk )

 VARIABLE CRC : std_logic_vector(15 DOWNTO 0) :=x"FFFF";
 VARIABLE data : std_logic_vector(7 DOWNTO 0);

BEGIN
 IF ( rst = '1' ) THEN
   finalCRC   <=  CRC;
   CRC        :=  x"FFFF";
   byte_count <=  count;
   bit_count  <=  0;
   count      <=  0;
   busy       <= '0';
   frame_done <= '1';
   crc_send   <= '0';
 ELSIF ( w_clk = '1' AND w_clk'EVENT ) THEN
    IF ( init = '1' ) THEN
       busy       <='0';
       CRC        := x"FFFF";
       count      <= 0;
       frame_done <= '0';
       bit_count  <= 0;
       crc_send   <= '0';
    ELSIF ( cs = '1' ) THEN
       busy                       <= '1';
       data                       := data_in;
       CRC(7 downto 0)            := CRC(7 downto 0) xor data;
       CRC(15 downto 8)           := CRC(15 downto 8);
       CRC                        := crc_calc(CRC);
       buffer1(count)(10)         <= '1';
       buffer1(count)(0)          <= '1';
       buffer1(count)(9)          <= not(data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0));
       buffer1(count)(8 downto 1) <= data;
       count                      <= count + 1;
    ELSIF ( WRITE = '1' AND crc_send = '0' ) THEN
       bit_out   <= buffer1(count)(bit_count);
       bit_count <= bit_count + 1;
       IF ( bit_count > 10 ) THEN
          count     <= count + 1;
          bit_count <= 0;
       ELSE
          null;
       END IF;
       IF(count > byte_count) THEN
          crc_send  <='1';
          count     <=0;
          bit_count <= 0;
       END IF;
    ELSIF ( WRITE = '1' AND crc_send = '1' ) THEN
      bit_out   <= finalCRC(bit_count);
      bit_count <= bit_count + 1;
      IF(bit_count > 15) THEN
        crc_send <= '0';
      END IF;
    END IF;
END PROCESS;
END Behavioral;
 
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