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Bad condition in wait statement, or only one clock per process

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ashwini012

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Hi,
I am now working on the some VHDL program,but i have faced the error:


Code VHDL - [expand]
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Sensor_fusion_1_output : PROCESS 
    VARIABLE z : vector_of_real(0 TO 11);
    VARIABLE xapriori : vector_of_real(0 TO 11);
    VARIABLE residual : vector_of_real(0 TO 11);
    VARIABLE papriori : vector_of_real(0 TO 11);
    VARIABLE K : vector_of_real(0 TO 11);
    VARIABLE paposteriori : vector_of_real(0 TO 11);
    VARIABLE xaposteriori1 : vector_of_real(0 TO 11);
    VARIABLE add_temp : real;
    VARIABLE div_temp : real;
    VARIABLE add_temp_0 : vector_of_real(0 TO 10);
    VARIABLE div_temp_0 : vector_of_real(0 TO 10);
 
  BEGIN
 
    z := temp;
    xapriori := (OTHERS => 0.0);
    residual := (OTHERS => 0.0);
    papriori := (OTHERS => 0.0);
    K := (OTHERS => 0.0);
    paposteriori := (OTHERS => 0.0);
    xaposteriori1 := (OTHERS => 0.0);
    xapriori(0) := 0.0;
    residual(0) := z(0);
    papriori(0) := 4.3;
    add_temp := 4.3 + 0.1;
 
    IF add_temp = 0.0 THEN 
      div_temp := C_divbyzero_p;
    ELSE 
      div_temp := One / add_temp;
    END IF;
      K(0) := div_temp;
      paposteriori(0) := 4.3 * (1.0 - K(0));
     xaposteriori1(0) := K(0) * z(0);
 
    FOR k_0 IN 0 TO 10 LOOP
      xapriori(1 + k_0) := xaposteriori1(k_0);
      residual(1 + k_0) := z(1 + k_0) - xapriori(1 + k_0);
      papriori(1 + k_0) := paposteriori(k_0) + 2.8;
      add_temp_0(k_0) := papriori(1 + k_0) + 0.1;
      IF add_temp_0(k_0) = 0.0 THEN 
        IF (papriori(1 + k_0) < 0.0) XOR (add_temp_0(k_0) < 0.0) THEN 
          div_temp_0(k_0) := C_divbyzero_n;
        ELSE 
          div_temp_0(k_0) := C_divbyzero_p;
        END IF;
      ELSE 
        div_temp_0(k_0) := papriori(1 + k_0) / add_temp_0(k_0);
      END IF;
 
      K(1 + k_0) := div_temp_0(k_0);
      paposteriori(1 + k_0) := papriori(1 + k_0) * (1.0 - K(1 + k_0));
      xaposteriori1(1 + k_0) := xapriori(1 + k_0) + (K(1 + k_0) * residual(1 + k_0));
    END LOOP;
 
   xaposteriori <= xaposteriori1;
 
    WAIT;
 
    END PROCESS Sensor_fusion_1_output;




I got the error as "Bad condition in wait statement, or only one clock per process."
Can any one help me please....

Thank you
 
Last edited by a moderator:

TrickyDicky

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I assume you know this code is not synthesisable as a single wait statement is no use for synthesis, it is for simulation only. So is the real type. This code looks far to much like software code, and hence will never work.

I suggest finding a good text book on digital logic design. Working through the exercises and starting your code again. Before you write any more code, you need to draw a circuit diagram. This is hardware description language, not programming.
 

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