Backdoor programming SPRAM in Verilog

[karthikw]

Hi,

I trying to do a backdoor loading of SPRAM, but I am not able write it externally ie I am reading 'X' once I write to the location . Please help me with it.

-Karthik

 

[sharath666]

Check whether your chip_en,clock as well as write_en is active during write. Check whether your write protocol is correct.

 

[karthikw]

Check whether your chip_en,clock as well as write_en is active during write. Check whether your write protocol is correct.

Thanks.

I am trying to access the RAM directly (ie two dimensional array verilog memory model) under reset. I am able to do a backdoor load with initial block in the same verilog model file but once I try to do it externally in the reset phase it doesn't. I am using a verilog model of memory does chip_en, clock and write_en matter?

-Karthik

 

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The memory model may check for X on either/both the address and write enable. Many of the models I've used force the array to Xs if either of those inputs go X.