Back-gate misalignment simulation using BSIM-IMG model

[oscarhung]

Hi,

I want to simulate the influence of back-gate misalignment using BSIM-IMG model. Is there any parameter I can modify in the verilog-A code or any convenient model card including misalignment parameter for BSIM-IMG code?

 

[dick_freebird]

What kind of back gate?

Planar SOI MOSFETs' back gate underlies the
whole device, so cannot be misaligned.

GAA FETs are another animal, as are tri-gate
FinFETs.

 

[oscarhung]

What kind of back gate?

Planar SOI MOSFETs' back gate underlies the
whole device, so cannot be misaligned.

GAA FETs are another animal, as are tri-gate
FinFETs.

Planar SOI MOSFET
I found some publications discussing back-gate misalignment if the back-gate is not defined by a self-aligned process. Or, it may be caused by the process variation. So is there any way to simulate this effect using BSIM-IMG SPICE models?