Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!
Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!
It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.
Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!
It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.
Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!
It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.
Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!
It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.