B10B Encoder/Decoder source code examples in Verilog

[s8319]

Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!

 

[nand_gates]

8b10b verilog

Here is 8b10b decoder code. Hope this may help you!

http://asics.chuckbenz.com/decode.v
http://asics.chuckbenz.com/encode.v

 

[maksya]

8b 10b encoding table

Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!

It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.

 

[ray123]

8b10b table

Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!

It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.

If I want to implement 64B/66B (or 64B/65B), will memory (LUT) still give better timings?

 

[maksya]

8b/10b table

Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!

It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.

If I want to implement 64B/66B (or 64B/65B), will memory (LUT) still give better timings?

I suppose it will be so. But nevetheless it will be usefull to check it in practice

 

[s8319]

8b/10b encoding table

Can anyone show me the 8B10B Encoder/Decoder source code examples in Verilog?
Which implementation architecture is better? Just using the look-up table or the circiuts introduced by the original IBM papers?
Thank you!

It depends on your optimization criteria. IMHO, memory (LUT) will give better timings, while combinational logic (implementation from IBM) demands less area.

Is the timing improvement achieved by the synthesis choice or just because of the LUT architecture?

 

[maksya]

8b 10b

Is the timing improvement achieved by the synthesis choice or just because of the LUT architecture?

LUT is just a memory. So, only read operation is required. And in the case of combinational logic we need to calculate new value of code.

 

[s8319]

8b/10b verilog

Is the timing improvement achieved by the synthesis choice or just because of the LUT architecture?

LUT is just a memory. So, only read operation is required. And in the case of combinational logic we need to calculate new value of code.

So you mean that usinng a 256 branch look up table? Not the 5b6b +3b4b stylre? that would be huge in area!

 

[maksya]

8b 10b encoding verilog

Is the timing improvement achieved by the synthesis choice or just because of the LUT architecture?

LUT is just a memory. So, only read operation is required. And in the case of combinational logic we need to calculate new value of code.

So you mean that usinng a 256 branch look up table? Not the 5b6b +3b4b stylre? that would be huge in area!

But faster!

 

[neoflash]

Re: 8B10B source code

How can I find 64/66b encoder/decoder and 128/130b encoder/decoder? Thanks.

 

[flylong]

Can anyone show me the 8b/10b Encoder using LUT?