AXI to AHB Interconnect

[derif]

Hi,

I am trying to build a multi-master AXI interconnect to a multi-slave AHB slave system. I would appreciate if I could get some hint on the implementation strucuture.

Here is what I think can be a possible candidate:

multiple AXI masters <-----> AXI Interconnect Fabric <------> Multi FIFO based AXI2AHB converter <------> AHB BUs <--> multi AHB slaves.

In this structure implementation regards, i had a few doubts:

1. AXI is a point-to-point protocol. So if there are 4 AXI master, then we need to have 4 individula AXI2AHB converter modules? similarly since the AHB is shared bus protocol, we can have upto 64 slaves supporting even a single master, without the constraint of having equal numbers of masters and slave, as in case of AXI interconnect,right?

2. There are two Shared Bus-type modules (AXI Interconnect fabric) and many individual AXI2AHB converters. The AXI2AHB converter acts as the main converter functional utility taking care of the actual conversion. The before and after shared bus systems are to facilitate the proper flow of transactions from right master to right slave.

3. The AXI interconnect acts as a decoder based on the ID of the master and slave by padding an extra field to these (described in sec 8.7 of AXI spec)

4. The AHB standard Bus is a normal multi master slave shared bus system which acts as a Decoder based on the slave address.


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AXI2AHB module:
1. How do I take care of the handshake in between these two protocols: AxVALID, AXREADY from AXI side and HREADY from AHB side?

2. How do I take care of WLAST and WSTRB to get WDATA from AXI properly synchronised with AHB DATA bus?

3. How do I take care of unalligned AXI data transfers?

4. Preserve AXI Non-overlapping data in right format at AHB side?

5. Exclusive locked transactions from AXI side to AHB?

6. When will my interconnect use IDLE, BUSY in HTRANS?

Thanks

 

[sree205]

can you please clarify one thing?

you've a multiple axi master - multiple ahb slave interconnect. At any point of time, how many axi masters & ahb slave combinations will be active?

 

[derif]

Since aXI interconnect permits multiple AXI master to communicate with multiple AXI slaves, and AHB bus interface permits/grants only one AHB master an access to only one AHB slave. So I assume that Multiple AXI masters can be active (though all their transactions will be saved in Buffer after the AXI interconnect) and depending upon the grant access, these will be accessing only 1 active AHB slave selected by AHB interface.

Please correct me if I am wrong.

Thanks,
Derif