Hi!
I want to find out delay of a 16 bit adder designed in cadence virtuso icfb tool for a large number of input values and Vdd. I know how to simulate the design with a given input and find delays using delay function in waveform calculator. How can I do this analysis for a large number of inputs, say 1000?
From one of your successful analyses you could create an ocean control file, then edit it for your input and supply voltage changes and have it run automatically. Or use SPICE .alter commands.
For - say - 1000 input sets, however, this could turn out as a cumbersome task - for both methods. Better use a statistical timing analysis (STA) tool for such a job: it would find the longest delay path(s) automatically. See e.g. this PDF.