ATPG simulation question!

[oashadhi]

Hi, all
i have a serious problem :
pre-layout scan ATPG simulation is good
post-layout scan ATPG simulation is error
both of them have no timing information (doesnt include sdf file and timing check)
scan reordering is done during layout
whats wrong?

 

[spauls]

looks like you ar enew to ASIC flow.

ATPG simulations make sense after scan chain stitching.

 

[oashadhi]

scan chain has been stiched after reordering
nothing is changed unless scan order after layout

 

[leeguoxian]

I had the same problem!

Dear oashadhi :
Have you figured out the reason?

 

[rameshsuthapalli]

hi
please refer my replies in the following link

 

[leeenghan]

Hi,

When you do not use sdf back-annotation, the delay of the cells are based on the delay in the ASIC library. It may not be zero, or 1ps. Please check the ASIC library (and the memories, etc) to understand what is the delay.

Sometime after clock tree insertion, the slew become very bad if you are using the ASIC lib delay. Then you can have hold violation.

If this is the case, the solution is to (1) change the delay in asic lib, or use the SDF.

In general, post-layout simulation does not run successfully in the first trial. However, looking at the waveform and simulation message (e.g. hold and setup violation) , you can figure what is wrong. There is always something new in every project, so don't be surprise; there is a need for technical skill to study the simulation result and correct the problem.

Regards,
Eng Han
www.eda-utilities.com