You can try zero-delay mode - it basically ignores any timing checks (in specify blocks of the cell models) - which with gate-level sim, is the only timing you should encounter. I think it is
-delay_mode zero
I haven't tried this lately, so for what it's worth...
Unfortunately, it's not that simple. Most cell libraries contain gate models with some sort of default timing specified, in a `specify block. This default timing is used, unless you explicitly tell the simulator not to use it. So then you say:
u can do ATPG simulation without using the SDF, it will be useful to basic sanity of u r ATPG patterns. when u r doing the simulation, u can enable the option no timing check in the tool