ATPG simulation question ?

[feel_on_on]

atpg simulation

I have generated pattern with TetraMax .But ,at present I still don't get a SDF file for simulation with NC-Verilog.

I want to know how to simuate without SDF file and get a right result ?

 

[dft_guy]

sdf atpg simulations

You can try zero-delay mode - it basically ignores any timing checks (in specify blocks of the cell models) - which with gate-level sim, is the only timing you should encounter. I think it is

-delay_mode zero

I haven't tried this lately, so for what it's worth...

John

 

[funzero]

ATPG may be run at 10M even 1Mhz , so dont worry about your design timing . just run atpg with not sdf file .

 

[dft_guy]

funzero,

Unfortunately, it's not that simple. Most cell libraries contain gate models with some sort of default timing specified, in a `specify block. This default timing is used, unless you explicitly tell the simulator not to use it. So then you say:

ATPG may be run at 10M even 1Mhz

That is true, but then if there happens to be hold time violations, it doesn't matter how slow you run it. The sim will fail...

John
DFT Digest

 

[kiranks9]

u can do ATPG simulation without using the SDF, it will be useful to basic sanity of u r ATPG patterns. when u r doing the simulation, u can enable the option no timing check in the tool