Hi,
I used the scan chain reordering flow introduce by synopsys. At last, I found design compiler didn't reorder the scan chain as that in the place and route tool. According to that flow, design compiler should reorder the scan chain after place and route as that in the place and route tool.
Before place and route, design complier writes the following.
dc_shell> set_scan_configuration -prtool avant
dc_shell> write_layout_scan -out design.def -noclockdomain
dc_shell> write -f db -hier cpu -out mydesign.db
dc_shell> write -f verilog -hier cpu -out mydesign.v
In Apollo, I detached the scan chian before preplacement, then connected that scan chain and optimized it after CTS.
Writes out the new scan reorder file
dbDumpScanChain (geGetEditCell) "scan.rpt"
After place and route, design compiler read the
dc_shell> set_scan_configuration -prtool avant
dc_shell> set_scan_configuration -prfile scan.rpt
dc_shell> set test_dont_fix_constraint_violations true
dc_shell> insert_dft -ignore_compile_design_rules
Do you have any comments?
Thanks for your kindful help.
Yawei