At-speed transition delay test patterns fail on ATE

[ajukrishnan]

Hi all,
I generated ATPG patterns for the current project and after serial simulation in best case and worst case corners, delivered them for ATE.The tool used was TetraMAX. There, the Stuck-at and the At-speed delay test pattern were failing initially.
After debug, we were suspecting power issues, and we generated quiet-chain-test patterns which does not toggle all the scan flops. They passed.
Later, we also could get the 2500 stuck-at patterns to pass almost till the end, where it fails. I suspect it is the few fast-sequential patterns in the end of the pattern set that fails. The atspeed patterns are all fast sequential, except first few. This pattern fails from the very beginning. Has anyone here had similar experiences? Can anybody help me in debugging and solving the issue of fast-sequential patterns failing on ATE?

Thanks in advance
Aju Krishnan

 

[rca]

1- double check, your simulation environement, do you have any analog/pad models which could have a different behavior? or do you ignore any thing from analog module?
2- check the timing propagation is properly annotated in your simulation
3- Based on the error, the tool could indicate if there is a "common" source of the issue (return to them the pattern failed...)

 

[rahul.achates]

Check for DFT reports generated from synthesis tool , there could be possibility , one of clock is not controllable in test mode.
Tool may pass all the checks but during simulation , some of test vector may fail because of unexpected switching of clock at one/more registers ... go through the architecture and go through all the clocks , make sure all clocks must be having a known clock in test mode (probably test clock).

let me know if this doesn;t work.
Rahul

 

[maulin sheth]

Hello Aju,
You can try run diagnosis flow of TetraMAX, to check the possibility of failures.
Have you run timing simulation with both Best case SDF and worst case SDF?

Thanks & Regards,
Maulin Sheth