module latch(reset_n, din, dout, en);
input reset_n, en;
input [7:0] din;
output [7:0] dout;
reg [7:0] dout;
always @(din or en or reset_n)
if (!reset_n)
dout = 1'b0;
else if (en)
dout = din;
endmodule // latch
module counter (ZRST, WR1, ADDR, DATA, QQ_CLK, QQ);
input [7:0] ADDR, DATA;
input ZRST, WR1, QQ_CLK;
output [7:0] QQ;
wire [7:0] QQ_latch;
wire en = (ADDR == 8'haa) ? WR1 : QQ_CLK;
wire [7:0] din = (ADDR == 8'haa) ? DATA : QQ_latch + 1;
latch latch0(ZRST, din, QQ, en);
latch latch1(ZRST, QQ, QQ_latch, ~en);
endmodule // counter
module counter_test();
reg [7:0] ADDR; // To counter of counter.v
reg [7:0] DATA; // To counter of counter.v
reg QQ_CLK; // To counter of counter.v
reg WR1; // To counter of counter.v
reg ZRST; // To counter of counter.v
wire [7:0] QQ; // From counter of counter.v
// End of automatics
counter counter(/*AUTOINST*/
// Outputs
.QQ (QQ[7:0]),
// Inputs
.ADDR (ADDR[7:0]),
.DATA (DATA[7:0]),
.ZRST (ZRST),
.WR1 (WR1),
.QQ_CLK (QQ_CLK));
initial begin
$shm_open("./WAVEFORM");
$shm_probe(counter_test, "AS");
ADDR = 8'haa;
DATA = 8'h55;
QQ_CLK = 1'b0;
WR1 = 1'b0;
ZRST = 1'b0;
# 10;
ZRST = 1'b1;
#100;
WR1 = 1'b1;
#2;
WR1 = 1'b0;
#10;
ADDR = 8'hbb;
#40;
QQ_CLK = 1'b1;
#2;
QQ_CLK = 1'b0;
#40;
WR1 = 1'b1;
#2;
WR1 = 1'b0;
#40;
QQ_CLK = 1'b1;
#2;
QQ_CLK = 1'b0;
#40;
DATA = 8'hCC;
#40;
QQ_CLK = 1'b1;
#2;
QQ_CLK = 1'b0;
#40;
QQ_CLK = 1'b1;
#2;
QQ_CLK = 1'b0;
#200;
$finish;
end
endmodule // counter_test