Asynchronous load in a register - DC code synthesis problems

[mediatek]

Is this verilog that can implement ckt function (see attach file waveform)

wire QQ_set; assign QQ_set = WR1 && (ADDR == 8’hAA);
always @(posedge QQ_CLK or negedge ZRST or posedge QQ_set)
if(!ZRST) QQ <= 8’h0;
// Reset signal
else if(QQ_set) QQ <= DATA;
// Asynchronous load
else QQ <= QQ + 1;

I use DC to synthesis
after simulation
it seems not the correct waveform that I want!
Is any verilog master can teach me what kind verilog RTL code can implement
CKT that I want!
TKS in advance!!

 

[eda_wiz]

rtl code for counter

THere is no concept of Asynchronous load in a register(except for the preset pin). so while synthesis DC considers QQ_set as a synchronous enable. but when QQ_set becomes one , there is no clock running so ur netlist simulation results are wrong.

I dont understnad why the QQ_clock occurs non periodically. If you are gating the clock with a signal , its better to do automatic clock gating with power compiler.

If you gate your clock simply with and gate, skew and combinational glitches might cause problems for you later in the design flow.

 

[mediatek]

rtl coding of clock gating

Many thanks to whizkid
but I dont know very clearly about your answer:

Q1 ,
THere is no concept of Asynchronous load in a register
==>Why in SOLD ver 2001.08 aug 2001
HDL COmpiler(Presto Verilog) reference manual
P 4-27 , I find D Filp-Flop with Asynchronous Load example?

Q2 . Yes " QQ_clock is a gated clock, could you please tell me more detail about how to do
"automatic clock gating with power compiler.
", is there any reference material or ebook to reference ?

Q3 If there is no clock between MCU I/F with My design block(only CS(chip sel), R/W , ALE), is there any better way (reference material/BOOK ..) to implement aync ckt to perform REGISTER R/W and MEM R/W feature, because I encounter many glitches problem after synthesis, and it will let my register/mem data r/w error ?

thanks for your help again!!

 

[rprince006]

about me rtl code

Hi there,

I am not a Verilog master, however, I am trying to figure out your problem.

For general Verilog design, all FF's will be automatically mapped to FF's of synchronous load, by the synthesis tools I think. To implement an asynchronously loaded DFF, you need to tell the synthesis tool to map your specific piece of code to it, and you should have an asynchronously loaded DFF in your Tech-Library.

I don't know how to do it exactly (cauze I never need to), you can look up the synthesizer's manual or ask them directly for support.

Good luck!

Rprince006

 

[nand_gates]

rtl latch set reset

Here is what you are looking for....
This code will synthesize...
But I dont know whether it will work on silicon or not!
Use it on ur own risk!

module latch(reset_n, din, dout, en);
   input reset_n,  en;
   input [7:0] din;
   output [7:0] dout;
   reg [7:0]   dout;
   always @(din or en or reset_n)
     if (!reset_n) 
       dout = 1'b0;
     else if (en) 
       dout = din;
endmodule // latch

module counter (ZRST, WR1, ADDR, DATA, QQ_CLK, QQ);
   input [7:0] ADDR, DATA;
   input       ZRST, WR1, QQ_CLK;
   output [7:0] QQ;
   wire [7:0]  QQ_latch;
   wire        en = (ADDR == 8'haa) ? WR1 : QQ_CLK;
   wire [7:0]  din = (ADDR == 8'haa) ? DATA : QQ_latch + 1;
   latch latch0(ZRST, din, QQ, en);
   latch latch1(ZRST, QQ, QQ_latch, ~en);
endmodule // counter


module counter_test();
   reg [7:0]          ADDR;                   // To counter of counter.v
   reg [7:0]          DATA;                   // To counter of counter.v
   reg                QQ_CLK;                 // To counter of counter.v
   reg                WR1;                    // To counter of counter.v
   reg                ZRST;                   // To counter of counter.v
   wire [7:0]           QQ;                     // From counter of counter.v
   // End of automatics
   counter counter(/*AUTOINST*/
                   // Outputs
                   .QQ                  (QQ[7:0]),
                   // Inputs
                   .ADDR                (ADDR[7:0]),
                   .DATA                (DATA[7:0]),
                   .ZRST                (ZRST),
                   .WR1                 (WR1),
                   .QQ_CLK              (QQ_CLK));

   initial begin
       $shm_open("./WAVEFORM");
       $shm_probe(counter_test, "AS");
       ADDR = 8'haa;
       DATA = 8'h55;
       QQ_CLK = 1'b0;
       WR1  = 1'b0;
       ZRST = 1'b0;
       # 10;
       ZRST = 1'b1;
       #100;
       WR1  = 1'b1;
       #2;
       WR1  = 1'b0;
       #10;
       ADDR = 8'hbb;
       #40;
       QQ_CLK = 1'b1;
       #2;
       QQ_CLK = 1'b0;
       #40;
       WR1  = 1'b1;
       #2;
       WR1  = 1'b0;
       #40;
       QQ_CLK = 1'b1;
       #2;
       QQ_CLK = 1'b0;
       #40;
       DATA = 8'hCC;
       #40;
       QQ_CLK = 1'b1;
       #2;
       QQ_CLK = 1'b0;
       #40;
       QQ_CLK = 1'b1;
       #2;
       QQ_CLK = 1'b0;
       #200;
       $finish;
   end
   
endmodule // counter_test

Hope this helps!

 

[eda_wiz]

synopsys presto synchronous reset

Q1 ,
THere is no concept of Asynchronous load in a register
==>Why in SOLD ver 2001.08 aug 2001
HDL COmpiler(Presto Verilog) reference manual
P 4-27 , I find D Filp-Flop with Asynchronous Load example?

>>A flip flop(register) input is loaded at clock edges. I dont have 2001.08 SOLD.
could u locate it in latest snug, I will check it in solvnet. or otherwise uplaod that document here . Another way of doing this is with latches(like nand_gates design) but this might cause lotsa trouble in DFT, STA etc.. so better not go for latches.

Q2 . Yes " QQ_clock is a gated clock, could you please tell me more detail about how to do
"automatic clock gating with power compiler.
", is there any reference material or ebook to reference ?

Usually in ASICs , simple AND clock gating circuits are not used.
Clock gating is done with negative latch based circuit.

always@(posedge clk or negedge rst)
begin
if(!rst)
q<=0;
else if (EN)//clock enable signal
q<=d;
end

if u write code like this and add

elaborate "design_name" -gate_clock

in your script. Powercompiler will insert the necesary ckt, ie the latch circuits required for efficient clock gating.

Checkout the attached document!!!

Q3 If there is no clock between MCU I/F with My design block(only CS(chip sel), R/W , ALE), is there any better way (reference material/BOOK ..) to implement aync ckt to perform REGISTER R/W and MEM R/W feature, because I encounter many glitches problem after synthesis, and it will let my register/mem data r/w error ?

If there is no clock , u need asynchronous circuits.... but I really wonder why there is no clock given to the peripheral block....

 

[mediatek]

synchronous reset power compiler verilog

Hi whizkid:
The attach file is HDL reference manual(v2003.03)
you can find Asyn load in p6-34~6-35

 

[Thomson]

clock gating flop verilog

Maybe you'd better to check your `timescale directive to make sure that you select the correct time accuracy to avoid the different negative and positive width of the clock waveform. Before you synthesize your codes, check the technology library first to confirm that the library contains the asynchronous reset and set registers(if robust, it always has). If the library does have, then the coding you described really can work; sometimes the following Verilog attributes may help to synthesize correctly:
The Verilog attributes for set and reset are:

// synopsys async_set_reset
// synopsys sync_set_reset
// synopsys async_set_reset_local
// synopsys sync_set_reset_local
// synopsys async_set_reset_local_all
// synopsys sync_set_reset_local_all


Sample Verilog code to infer a synchronous set flip-flop and a synchronous reset flip-flop:
----------------------------------------------------------------------------------------

module sync_set_reset(clk, reset, set, d1, d2, y, t) ;
input clk, reset, set, d1, d2 ;
output y, t ;
// synopsys sync_set_reset "reset, set"
reg y, t ;
always @ (posedge clk)
begin : synchronous_reset
if (reset)
y = 1'b0; // synchronous reset
else
y = d1;
end
always @ (posedge clk)
begin : synchronous_set
if (set)
t = 1'b1; // synchronous set
else
t = d2;
end
endmodule


Verifying that the attributes were correctly applied
----------------------------------------------------

Before you read the HDL code, set the Design Compiler variable

hdlin_report_inferred_modules = verbose

to get a complete inference report of the sequential cells. After you
read in the HDL, check the inference report to see that the attributes
were correctly applied.