tia_design
Advanced Member level 4
assura lvs form
I have a digital circuit in Verilog systhesized netlist and a layout generated by place and layout tool. Now I want to do LVS using Assura in Virtuso Layout tool. So how should I set up the Assura LVS form. Just select the netlisf file and layout view? After I did this, I was told there is no information about basic gate, like AND gate and FlipFlop.
Some people said using CDL file, but how to get CDL file? Thanks!
I have a digital circuit in Verilog systhesized netlist and a layout generated by place and layout tool. Now I want to do LVS using Assura in Virtuso Layout tool. So how should I set up the Assura LVS form. Just select the netlisf file and layout view? After I did this, I was told there is no information about basic gate, like AND gate and FlipFlop.
Some people said using CDL file, but how to get CDL file? Thanks!