Assura LVS using Verilog synthesized netlist

[tia_design]

assura lvs form

I have a digital circuit in Verilog systhesized netlist and a layout generated by place and layout tool. Now I want to do LVS using Assura in Virtuso Layout tool. So how should I set up the Assura LVS form. Just select the netlisf file and layout view? After I did this, I was told there is no information about basic gate, like AND gate and FlipFlop.

Some people said using CDL file, but how to get CDL file? Thanks!

 

[kumar_eee]

lvs with assura for digital

You can generate CDL netlist by using Virtuoso.. In Virtuoso, you can export cdl nelist for all kind of schematic circuit.