in this point i wanna ask one question.
currently any tools works on behavioural level synthesis.
like i wanna assign a value after some delay only.
a <= #5 b
whether any synthesis tools works on this logic?
synthesis tools can work on this logic, but in the synthesis process, the delay time in this code will be ignored, and this will result in the dismatch of functional verification from timing verification
There are far better ways of modellng delay then in assign statememt . If you are tring to model the transport delay then using #delay and assign statement will model it wrongly! . There was already a post on delay modeling
hi,
we use as delay as particular time limit when any process execute with in time of delay.
example for gate
or #2 u1(a,b, out);
and #1 u2(a, b, out);
this means that first gate execute for 2 time delay. After the second gate execute for 2+1 time delay.
For the more information use the book of verilog hdl author is James M. Lee.
i think it will help u.