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assignment statement in Verilog

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Member level 1
Jan 13, 2006
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I read in somewhere stating that delay should not be included in assignment statement.
assign c = a & b;

Instead of
assign #0.3 c = a & b;

Can anyone tell me what is the reason? There shoud be some delay in any gates rite? But why delay is not included?

delays can be used and is legal. but it is used mainly in modelling. During RTL coding this has to be avoided

delays can be used for modelling but synthesis tools ignore the delays.

it has include the delay and it is very small

in this point i wanna ask one question.
currently any tools works on behavioural level synthesis.
like i wanna assign a value after some delay only.
a <= #5 b
whether any synthesis tools works on this logic?

synthesis tools can work on this logic, but in the synthesis process, the delay time in this code will be ignored, and this will result in the dismatch of functional verification from timing verification

a delay can be simulated but it can't be synthesized so it is generally best to avoid delays while coding

It is a just a wire when we use assignment
or else we can write
wire c = a & b ;

You may have pre and post sim mismatch.

There are far better ways of modellng delay then in assign statememt . If you are tring to model the transport delay then using #delay and assign statement will model it wrongly! . There was already a post on delay modeling


we use as delay as particular time limit when any process execute with in time of delay.
example for gate
or #2 u1(a,b, out);
and #1 u2(a, b, out);
this means that first gate execute for 2 time delay. After the second gate execute for 2+1 time delay.
For the more information use the book of verilog hdl author is James M. Lee.
i think it will help u.

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