[SOLVED] Assessing MOSFET parasitics

[JEOvergaard]

Dear everyone

I am currently in midst of designing an integrated switched capacitor converter. But I am having some difficulties assessing MOSFET parasitic capacitances. This both goes for a single NMOS but also CMOS inverters. I am using TSMC018 in Cadence Spectre, to anyone wondering.

I have some ideas on how to do it, but I am not sure, which one is the better. First for a single NMOS transistor I would do one of the following:

1. DC bias operating point parameter cgg (supposingly the sum of all capacitive parasitics at the gate, biasing with 5 V since it will be driven with 5 V. The capacitance naturally varies with applied Vgs.
2. AC analysis: Biasing the gate with a 1 - 100 H inductor at 5 V and then supplying a 1 A AC current source directly to the gate measuring the resulting magnitude and calculating the capacitance based on magnitude and frequency.
3. Transient analysis: Biasing the gate with a 1 - 100 H inductor at 5 V. Then I supply a constant current of 1 A and calculate the slope with ViVA. Then i use: i = C * dv/dt to calculate C.

For a W/L = 119mm/400nm MOSFET, the results i get from the mentioned analyses sum up to: 545 pF (DC bias), 564 pF (transient, constant current) and 645 pF (AC analysis).

All in all the three methods show quite similar results, but I would like to learn, how I should and shouldn't be doing this parasitic extraction. For a CMOS inverter I'd suppose it differs if you bias it with a 0 V or 5 V voltage source. Even doing so for a single NMOS transistor makes the capacitance vary quite a bit.

Best regards Jacob.

 

[frankrose]

My thoughts:
1. DC is good, but Vd value is important to get the proper Cgg.
2. AC is better if you don't use an inductor just a vdc from analogLib and set the AC magnitude to 1V for it. You can save the gate current, and from the frequency you can calculate the Cin. Vd also matters here and the used frequency too because the Cgs is frequency dependent.
3. In transient the slope changes because your device changes regions with the changing Vgs (linear, subthreshold, saturation). At different Vgs voltages the Cgs is else, also the Cgs depends from the speed of the slope. This method is not too good I think.

 

[JEOvergaard]

My thoughts:
1. DC is good, but Vd value is important to get the proper Cgg.
2. AC is better if you don't use an inductor just a vdc from analogLib and set the AC magnitude to 1V for it. You can save the gate current, and from the frequency you can calculate the Cin. Vd also matters here and the used frequency too because the Cgs is frequency dependent.
3. In transient the slope changes because your device changes regions with the changing Vgs (linear, subthreshold, saturation). At different Vgs voltages the Cgs is else, also the Cgs depends from the speed of the slope. This method is not too good I think.

Hi frankrose, thank you very much for your reply, I greatly appreciate it!

1. Naturally the Vd must be set properly, actually just realised I set it incorrectly in my case. Used 5 V when I should be using 20 V actually.
2. Hmm, I would need to set a DC voltage to set its DC operating region, ideally at least, wouldn't? I'd suppose so since sweeping the DC operating point parameter cgg changes with Vgs applied, but I am not entirely sure on this, and the literature is quite scarce on this area.
3. Ah, you are absolutely right, that makes sense. But I'd assume having a DC voltage of 5 V before DC current is supplied (insuring a set operating region that is defined, saturation here) would solve the issue.

 

[frankrose]

1. I don't remember I saw 20V devices in TSMC018 foundry. Nice if they have.
2. You can set the DC value of a vdc source and you can also set the AC magnitude for it. Check it at the properties. Anyway you are absolutely right, you should set the operating point. But you don't need inductor to couple DC voltage to the gate. That was the point.
3. It seems to a not valid test around the operating point. It is totally large signal analysis. To calculate Cin or Cgg usually small signal analysis is the straightforward.

 

[JEOvergaard]

1. TSMC foundry has 24 V devices and 36 V. Currently I'm using the 36 V version due to better muCox, otherwise I'd need some shit large transistors.
2. Right, of course.
3. You might be right about this.

Time will tell if it works. This will largely be based on the behaviour of my future gate-driver though.

Thanks for your assistance and input frankrose, I greatly appreciate it.