ASSEMBLE DESIGN -Physical Design using CADENCE SOC ENCOUNTER

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viswanadh_babu

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Hai All,


In toplevel design , we use lefs of partition blocks . After performing the assemble design ,
and saving it, even though the design is flat the partition lef is being reflected. Why?


Anyone Can explain This .

Thnaks in advance
K.VISWANADH BABU
 

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