asking for comment on 2-phase clock, latch design style

[asicer]

Does anyone has experience with ASIC design with latch and two phase clock? I though it may save area using latches. The two phase clock scheme can handle the timing problem with latch. What I don't know is whether it can be employed in the ASIC design flow using Synopsys tools. Would anyone like to comment on the timing check and DFT of the design style?