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ask for voltage independent delay cell

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Member level 5
Jun 15, 2006
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as the pic shows , i design a delay cell by long channel length MOS, but the delay time is variant by VLV .
Is any possible we can design a simple circiut by only simple modified inverter and it won't be infleuence by Vcc ?

It is very important , since we need to appy at deadtime control on power supply application.

Ask for Help ....pleeeeze

One possible method would be using current sources at the sources of both the NMOS and the PMOS (of equal currents of course) and using the NMOS and PMOS devices to switch the currents. But this is not a simple solution as you'll need to implement a current source.

Yes, you's want to move to a current-starved inverter
design with a master reference whose tempco and
supply_voltco produces a flat delay profile -at the
point of interest- (logic delay dead flat, plus driver taper
chain delay not-flat, would still not be uniform; your
logic delay might need to have a counter-slope for a
net flat result).

So following this train of thought, perhaps you only need
to have one delay-comp block and let the rest of the chain
be simple. That's a better outcome for routability and
such, if you can make it work.

Or, you could make a deadband (anti-shoot-through?)
scheme that is not "ballistic" but based on sensing the
transition further down the chain on the opposite leg,
then you will adapt to the situation without embedding
so much guessing or assumptions about tolerances and

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