anjali
Full Member level 3
hello,
i have done ASIC synthesis on my design using dc. and i have done FPGA synthesis using synplifyPro on the same design.
i have simulated the ASIC synthesized netlist & all test vectors are passed. and i have simulated the FPGA synthesized netlist, but in this case, some test vectors are failed.
can anybody explain, why it is so?
i have done ASIC synthesis on my design using dc. and i have done FPGA synthesis using synplifyPro on the same design.
i have simulated the ASIC synthesized netlist & all test vectors are passed. and i have simulated the FPGA synthesized netlist, but in this case, some test vectors are failed.
can anybody explain, why it is so?