hello,
i have done ASIC synthesis on my design using dc. and i have done FPGA synthesis using synplifyPro on the same design.
i have simulated the ASIC synthesized netlist & all test vectors are passed. and i have simulated the FPGA synthesized netlist, but in this case, some test vectors are failed.
Anjali, You will need to be somewhat more specific about the Test Vectors that failed on SynplifyPro and the warnings or errors thus generated. Reason being DC and Synplify use different optimization strategies. And FPGAs have got some restrictions regarding the RTL which is to be synthesized. So, You should look for the constraints, Optimzation goals, Libraries used and Synthesis properties.