Not sure what the option is called in Modelsim, but look for hierarchy-related option when exporting. Maybe it is called scope or similar. Should be pretty easy to find.
Thanks so much for your reply.
My problem is not the other signals in the other hierarchy level don't appear. The problem is the signals in the same top level don't all appear.
I use those commands:
power add testbench/switch_ins/*
power report -all -bsaif result.saif
and here the top level is "switch_ins" and I can't see all the signals in this level appear in the saif file.
What about optimization do you have it enabled on the level that you are trying to capture? Try setting the optimization to make all the signals visible in that block.
It is better to use formatting like bold and color the text red, so as not to introduce what would be a syntax error.
Not sure what DC would expect the signal to look like . is a perfectly acceptable character for hierarchy in Verilog, though I have no clue if it's acceptable as an SAIF separater. Maybe it's expecting the separator to be a / or _ or something else entirely.
I have a vague recollection that Modelsim allows you to modify the separator used when writing out files that contain names with hierarchy, I think it was something in the .ini file, but I'm not sure (and I don't have the time to research it right now).