ASIC switching activity

[Thawra-Kadeed]

Hello,

I would like to create improve the power estimation using power activity.
I use Modelsim and design compiler, the question is:

How can I use Modelsim to dump all the signals in the saif file?

Because my problem now I can't see all the signals in the saif file, I see just part of them and the other part is very important for my work.

Thanks in advance for your help

 

[ThisIsNotSam]

Not sure what the option is called in Modelsim, but look for hierarchy-related option when exporting. Maybe it is called scope or similar. Should be pretty easy to find.

 

[Thawra-Kadeed]

Thanks so much for your reply.
My problem is not the other signals in the other hierarchy level don't appear. The problem is the signals in the same top level don't all appear.
I use those commands:

power add testbench/switch_ins/*

power report -all -bsaif result.saif

and here the top level is "switch_ins" and I can't see all the signals in this level appear in the saif file.

Do you have any explanation for that?

Thanks

 

[ads-ee]

What about optimization do you have it enabled on the level that you are trying to capture? Try setting the optimization to make all the signals visible in that block.

 

[Thawra-Kadeed]

Thanks a lot for your reply.

Unfortunately it's the same, but I tried Questasim rather than Modelsim and it worked and I saw the important data signal in the output like:

(data_in\[0\] . data\[0\] (T0 6) (T1 1990) (TX 4) (TC 1) (IG 0))

But when I tried to read this saif file in the synopsys design compiler, I had an error says:

Illegal character at or near token ' . ' (SAIF-5)

DC doesn't accept the ' . ' symbol in the data signal which I already mentioned.

Does any one have any idea about that?!!!!

Thanks

 

[Thawra-Kadeed]

I put this space just to make the error clear for you, but no in reality there is no space.

I was wondering whether using prime time in more helpful. But I also need DC to make the synthesis and this needs the ready saif file before.

I hope any one here has an idea about that.
Thanks

 

[ads-ee]

Is this the signal name as it exists in the output or is this a cut and paste typo?

data_in\[0\] . data\[0\]
            ^ ^ <<<< there are spaces around the .

spaces aren't legal in a hierarchical name in any tool I've worked with.

- - - Updated - - -

I put this space just to make the error clear for you, but no in reality there is no space.

It is better to use formatting like bold and color the text red, so as not to introduce what would be a syntax error.

Not sure what DC would expect the signal to look like . is a perfectly acceptable character for hierarchy in Verilog, though I have no clue if it's acceptable as an SAIF separater. Maybe it's expecting the separator to be a / or _ or something else entirely.

I have a vague recollection that Modelsim allows you to modify the separator used when writing out files that contain names with hierarchy, I think it was something in the .ini file, but I'm not sure (and I don't have the time to research it right now).