Ramesh Vallimuthu
Newbie level 3
Why cant we use PERL for asic design verification as it has very good features as compared to System verilog?
Some important features of System verilog :
Features inherited from Verilog HDL,VHDL,C
Constrained-random stimulus generation
Functional coverage
Interfaces
Assertions
Higher-level structures, especially object-oriented programming
Multithreading and interprocess communication
Support for HDL types such as Verilog?s 4-state values
Same features as System verilog in PERL :
can write package to link verilog HDL,VHDL,c
can write package for constraint random stimulus generation
interprocess communication
oops concept
can write package for coverage
tools for system administration tasks
powerful string-manipulation functions
Please any one reply.
Some important features of System verilog :
Features inherited from Verilog HDL,VHDL,C
Constrained-random stimulus generation
Functional coverage
Interfaces
Assertions
Higher-level structures, especially object-oriented programming
Multithreading and interprocess communication
Support for HDL types such as Verilog?s 4-state values
Same features as System verilog in PERL :
can write package to link verilog HDL,VHDL,c
can write package for constraint random stimulus generation
interprocess communication
oops concept
can write package for coverage
tools for system administration tasks
powerful string-manipulation functions
Please any one reply.