ARM AHB/APB question

[vcnvcc]

I have question on AHB Bus –

Question – 1 (related to issue faced in closing timing.)
Basically I am new to ARM & its Bus protocol, I have just started to work on it, so have lot of questions.

I am referring to this diagram e.g . **broken link removed**

Can I say that arbiter + muxes + decode selection – all these “overall matrix” is a big combinational block?
If yes, lets say big designs where we have e.g. 6 masters and 15 slaves, in that case “overall matrix” will be very big and complex, now here how do I close timing? Provided I can go back and change architecture/RTL…..Because overall matrix will be big combo circuit…


Question 2- (related to evlolution of APB to AHB to layered AHB??(don’t know layered/multi layered concept) to AXI )

I have checked and somewhat understood AHB – APB systems, but what is layered. I read about multi layer AHB/AXI – so what is that, how this thing came into picture? Why ARM proposed multilayer concept?

Appreciate if you share your insights and experience as well.


Thanks!!

 

[Ashish Agrawal]

I have question on AHB Bus –

Question – 1 (related to issue faced in closing timing.)
Basically I am new to ARM & its Bus protocol, I have just started to work on it, so have lot of questions.

I am referring to this diagram e.g . **broken link removed**

Can I say that arbiter + muxes + decode selection – all these “overall matrix” is a big combinational block?
If yes, lets say big designs where we have e.g. 6 masters and 15 slaves, in that case “overall matrix” will be very big and complex, now here how do I close timing? Provided I can go back and change architecture/RTL…..Because overall matrix will be big combo circuit…

I don't think arbiter is a combinational block. I suggest you to refer the ARM documents and see the waveforms how request and grant mechanism works.
Arbiter doesn't generate the HMASTER signal in the same cycle when it gets request from master. So HMASTER can be a flop output. Which is used for mux selection.

Regards,
Ashish

 

[dpaul]

Can I say that arbiter + muxes + decode selection – all these “overall matrix” is a big combinational block?

If you take the overall interconnect into account, yes, in my opinion you may view it as a large combinatorial block.
But why are you getting worried before implementing your design? Are you designing your own interconnect?
In that case you might inadvertently introduce long combi. paths. So you have to be cautious from the RTL design stage.
Do the timing analysis and then see if there are any timing violations! Generally most designers use an IP block for such purposes (to reduce time-to-market) which is designed in such a way that long combi. paths are cut down, so that timing violations do not occur.

Question 2- I read about multi layer AHB/AXI – so what is that, how this thing came into picture? Why ARM proposed multilayer concept?

This question can be best answered by someone who has architect level experience. I will try, but don't completely rely on this.
Multi-layer AHB is an interconnection scheme which allows for parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth as well as a more flexible choice of system architecture.
In situations where the system bottleneck is the result of limited bandwidth across the system bus, Multi-layer AHB solves the issue by multiplying the available bandwidth in proportion to the number of bus layers. Additional benefits arise from the
reduction in bus transaction latency as a result of the increased bus capacity.

 

[vcnvcc]

Thank you Guys for your reply!!

Generally most designers use an IP block for such purposes (to reduce time-to-market) which is designed in such a way that long combi. paths are cut down, so that timing violations do not occur.

Yes.. That caught my interest, how that paths are cut down?
- is that something which even we come across called pipe-lining? to fix timing at RTL?

or some other concept which has been implemented to fix timing for such huge combo??

 

[ads-ee]

Yes.. That caught my interest, how that paths are cut down?
- is that something which even we come across called pipe-lining? to fix timing at RTL?

That's what you do add registers in the big combo logic to pipeline the operation. You trade long combo delays and slow clock frequencies with multiple clock edge latency and higher clock frequencies.